Merge branch 'main' into topic/extdbg-updates

Signed-off-by: Ravi Sahita <[email protected]>

chapter6.adoc

@@ -309,7 +309,10 @@ operations requested through `control.OP`.
   {bits: 24, name: 'SRC_ID'},
   {bits:  8, name: 'IOMMU_ID (WARL)'},
   {bits:  8, name: 'SDID (WARL)'},
-  {bits: 16, name: 'WPRI'}
+  {bits:  4, name: 'SRL'},
+  {bits:  4, name: 'SML'},
+  {bits:  4, name: 'SQRID'},
+  {bits:  4, name: 'WPRI'}
 ], config:{lanes: 8, hspace:1024}}
 ....
 
@@ -436,6 +439,13 @@ rule.
 The `SDID` field identifies the supervisor domain whose memory is accessed by
 this transaction.
 
+The `SRL` and `SML` fields along with `operand-1.SSM` field are used to determine
+the effective `RCID` and `MCID` provided by the IOMMU for device originated
+requests. The determination of the effective `RCID` and `MCID` is as specified
+by <<SMQOSID>>. The `SQRID` identifies the QRI for requests originating from the
+devices associated with the SD and accompanies the `RCID` and `MCID` in the
+requests made by the device to the QRI.
+
 [[OP-1]]
 === Operand 1 register (`operand-1`)
 
@@ -450,7 +460,8 @@ operations requested through `control.OP`.
   {bits:  4, name: 'MTT_MODE (WARL)'},
   {bits:  1, name: 'PPNV (WARL)'},
   {bits:  1, name: 'S (WARL)'},
-  {bits:  4, name: 'WPRI'},
+  {bits:  1, name: 'SSM'},
+  {bits:  3, name: 'WPRI'},
   {bits: 44, name: 'PPN'},
   {bits: 10, name: 'WPRI'}
 ], config:{lanes: 8, hspace:1024}}

chapter7.adoc

@@ -211,16 +211,26 @@ that cause a M-level supervisor domain external interrupt. The enable bits in
 `msdeie` do not affect the S- and VS-level external interrupt pending signals
 from the interrupt controller selected by `msdcfg.SDICN`.
 
-=== Machine Interrupt registers (`mip` and `mie`)
-
-The `Smsdia` extension introduces the machine supervisor domain external
-interrupt-pending (`MSDEIP` - bit 32) field in `mip` and the machine supervisor
-domain external interrupt-enable (`MSDEIE` - bit 32) field in `mie`. The
-`MSDEIP` bit is read-only, and is 1 if and only if the bitwise logical AND of
-CSRs `msdeip` and `msdeie` is nonzero in any bit.
-
-Multiple simultaneous interrupts destined for M-mode are handled in the
-following decreasing priority order: MEI, MSI, MTI, MSDEI, SEI, SSI, STI.
+=== Machine and Supervisor Interrupt registers (`mip/mie` and `sip/sie`)
+
+The `Smsdia` extension introduces the local supervisor domain external
+interrupt-pending (`LSDEI`). This interrupt is treated as a standard local
+interrupt that is assigned to bit 16 in the `mip`, `mie`, `sip`, and `sie`
+registers. The bit 16 in `mip` and `sip` is called `LSDEIP` and the same bit in
+`mie` and `sie` is called `LSDEIE`. The `mideleg` register controls the
+delegation of `LSDEI` interrupt to S-mode. This interrupt cannot be delegated to
+VS-mode and the the bit 16 of `hideleg` is read-only zero.
+
+The `mip.LSDEIP` bit is read-only, and is 1 if and only if the bitwise logical
+AND of CSRs `msdeip` and `msdeie` is nonzero in any bit. The `sip.LSDEIP` bit is
+read-only, and is 0 if `LSDEI` is not delegated to S-mode otherwise it returns
+the value of the `mip.LSDEIP` when read.
+
+Multiple simultaneous interrupts destined for different privilege modes are
+handled in decreasing order of destined privilege mode. Multiple simultaneous
+interrupts destined for the same privilege mode are handled in the following
+decreasing priority order: high-priority RAS event, MEI, MSI, MTI, SEI, SSI,
+STI, LSDEI, SGEI, VSEI, VSSI, VSTI, LCOFI, low-priority RAS event.
 
 [NOTE]
 ====
@@ -230,4 +240,12 @@ supervisor domain that has a supervisor domain interrupt controller directly
 assigned to it, the RDSM updates the `msdcfg.SDICN` to select that interrupt
 controller and may clear the bit corresponding to that interrupt controller in
 `msdeie` prior to resuming execution of the supervisor domain.
+
+The RDSM may delegate `LSDEI` to a supervisor domain that may be entrusted by
+the RDSM to get notified about supervisor domain external interrupts pending for
+one or more other supervisor domains. Typically, this use case involves a single
+supervisor domain that is trusted by the RDSM to receive such notifications. The
+delegation supports optimizing the exit sequence from such supervisor domain by
+enabling such supervisor domains to voluntarily yield execution in response to
+pending interrupts for the other supervisor domains.
 ====