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HACK: cutoff something and rebase the 20180919
Rebase on the rockchip inside kernel: d250b6b (BACKPORT: usb: gadget: composite: make sure to reactivate function on unbind) Change-Id: I4f405f5295d0c681be10f9139074aae917c8162d Signed-off-by: Caesar Wang <[email protected]>
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@@ -45,6 +45,7 @@ Module.symvers | |
/boot.img | ||
/kernel.img | ||
/resource.img | ||
/zboot.img | ||
/tags | ||
/TAGS | ||
/linux | ||
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@@ -276,6 +276,7 @@ What: /sys/devices/system/cpu/vulnerabilities | |
/sys/devices/system/cpu/vulnerabilities/meltdown | ||
/sys/devices/system/cpu/vulnerabilities/spectre_v1 | ||
/sys/devices/system/cpu/vulnerabilities/spectre_v2 | ||
/sys/devices/system/cpu/vulnerabilities/spec_store_bypass | ||
Date: January 2018 | ||
Contact: Linux kernel mailing list <[email protected]> | ||
Description: Information about CPU vulnerabilities | ||
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@@ -101,6 +101,7 @@ Date: February 2015 | |
Contact: "Jaegeuk Kim" <[email protected]> | ||
Description: | ||
Controls the trimming rate in batch mode. | ||
<deprecated> | ||
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What: /sys/fs/f2fs/<disk>/cp_interval | ||
Date: October 2015 | ||
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56
Documentation/devicetree/bindings/display/rockchip/rockchip_mipi_csi_tx.txt
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Rockchip MIPI CSI HOST | ||
================================ | ||
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Required properties: | ||
- compatible: must be one of: | ||
"rockchip,rk1808-mipi-csi". | ||
- reg: Represent the physical address range of the controller. | ||
- interrupts: Represent the controller's interrupt to the CPU(s). | ||
- clocks, clock-names: Phandles to the controller's APB clock(pclk) as | ||
described in [1]. | ||
- resets : phandle to the reset of MIPI CSI APB Clock. | ||
- reset-names : should be "apb". | ||
- rockchip,grf: this soc should set GRF regs to mux vopl/vopb. | ||
- #address-cells: Should be <1>. | ||
- #size-cells: Should be <0>. | ||
- ports: contain a port node with endpoint definitions as defined in [2]. | ||
For vopb,set the reg = <0> and set the reg = <1> for vopl. | ||
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Optional properties | ||
- clocks, clock-names: | ||
phandle to the SNPS-PHY config clock, name should be "phy_cfg". | ||
phandle to the SNPS-PHY PLL reference clock, name should be "ref". | ||
phandle to the Non-SNPS PHY high speed clock, name should be "hs_clk". | ||
phandle to the h2p bridge clock, name should be "h2p". | ||
- phys: phandle to Non-SNPS PHY node | ||
- phy-names: the string "mipi_dphy" when is found in a node, along with "phys" | ||
attribute, provides phandle to MIPI PHY node | ||
- rockchip,dual-channel: for dual-channel panel, if not, don't configure | ||
- rockchip,lane-rate: manually configure lane-rate, not necessary. | ||
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
[2] Documentation/devicetree/bindings/media/video-interfaces.txt | ||
[3] Documentation/devicetree/bindings/reset/reset.txt | ||
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Example: | ||
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For Rockchip RK1808: | ||
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csi: csi@ffb20000 { | ||
compatible = "rockchip,rk1808-mipi-csi"; | ||
clocks = <&cru PCLK_MIPI_CSI0>, <&mipi_dphy>; | ||
clock-names = "pclk", "hs_clk"; | ||
phys = <&mipi_dphy>; | ||
phy-names = "mipi_dphy"; | ||
resets = <&cru SRST_MIPICSI>; | ||
reset-names = "apb"; | ||
... | ||
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ports { | ||
port { | ||
csi_in_vop: endpoint { | ||
remote-endpoint = <&vop_out_csi>; | ||
}; | ||
}; | ||
}; | ||
}; |
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