Merge pull request #16 from sifive/JTAG_bus_def

added JTAG busDef

specs/sifive.com/TEST/JTAG/0.1.0/JTAG_rtl.json5

@@ -0,0 +1,56 @@
+{
+  abstractionDefinition: {
+    vendor: 'sifive.com',
+    library: 'TEST',
+    name: 'JTAG_rtl',
+    version: '0.1.0',
+    busType: {
+      vendor: 'sifive.com',
+      library: 'TEST',
+      name: 'JTAG',
+      version: '0.1.0',
+    },
+    ports: {
+      TCK: {
+        description: 'Clock',
+        requiresDriver: true,
+        isClock: true,
+        wire: {
+          onMaster: {width: 1, direction: 'out', presence: 'required'},
+          onSlave:  {width: 1, direction: 'in', presence: 'required'}
+        }
+      },
+      TMS: {
+        description: 'Mode Select',
+        wire: {
+          onMaster: {width: 1, direction: 'out', presence: 'required'},
+          onSlave:  {width: 1, direction: 'in', presence: 'required'}
+        }
+      },
+      TDI: {
+        description: 'Data Input',
+        isData: true,
+        wire: {
+          onMaster: {width: 1, direction: 'out', presence: 'required'},
+          onSlave:  {width: 1, direction: 'in', presence: 'required'}
+        }
+      },
+      TDO: {
+        description: 'Data Output',
+        isData: true,
+        wire: {
+          onMaster: {width: 1, direction: 'in', presence: 'required'},
+          onSlave:  {width: 1, direction: 'out', presence: 'required'}
+        }
+      },
+      TRST: {
+        description: 'Reset',
+        isReset: true,
+        wire: {
+          onMaster: {width: 1, direction: 'out'},
+          onSlave:  {width: 1, direction: 'in'}
+        }
+      },
+    }
+  }
+}