add inline blackbox to PowerOnResetFPGAOnly.

src/main/scala/ip/xilinx/Xilinx.scala

@@ -4,6 +4,7 @@ package sifive.fpgashells.ip.xilinx
 import Chisel._
 import chisel3.{Input, Output}
 import chisel3.experimental.{Analog, attach}
+import chisel3.util.HasBlackBoxInline
 import freechips.rocketchip.util.{ElaborationArtefacts}
 
 import sifive.blocks.devices.pinctrl.{BasePin}
@@ -80,11 +81,29 @@ class reset_mig extends BlackBox {
 
 // This is a FPGA-Only construct, which uses
 // 'initial' constructions
-class PowerOnResetFPGAOnly extends BlackBox {
+class PowerOnResetFPGAOnly extends BlackBox with HasBlackBoxInline {
   val io = new Bundle {
     val clock = Input(Clock())
     val power_on_reset = Output(Bool())
   }
+  setInline("",
+    """// See LICENSE file for license details.
+      |(* keep_hierarchy = "yes" *) module PowerOnResetFPGAOnly(
+      |  input clock,
+      |  (* dont_touch = "true" *) output power_on_reset
+      |);
+      |  reg reset;
+      |  assign power_on_reset = reset;
+      |
+      |  initial begin
+      |     reset <= 1'b1;
+      |  end
+      |
+      |  always @(posedge clock) begin
+      |     reset <= 1'b0;
+      |  end
+      |endmodule
+      |""".stripMargin)
 }
 
 object PowerOnResetFPGAOnly {