fix is_pending logical error (#144)

stm32-rs · Mar 17, 2024 · 096121a · 096121a
1 parent ebf0a15
commit 096121a
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/exti.rs b/src/exti.rs
@@ -169,7 +169,7 @@ impl ExtiExt for EXTI {
             SignalEdge::Rising => self.rpr1.read().bits() & mask != 0,
             SignalEdge::Falling => self.fpr1.read().bits() & mask != 0,
             SignalEdge::All => {
-                (self.rpr1.read().bits() & mask != 0) && (self.fpr1.read().bits() & mask != 0)
+                (self.rpr1.read().bits() & mask != 0) || (self.fpr1.read().bits() & mask != 0)
             }
         }
     }