Prepare for hrtim

.github/workflows/ci.yml

@@ -1,6 +1,6 @@
 on:
   pull_request:
-  
+
 name: Continuous integration
 
 # Make sure CI fails on all warnings, including Clippy lints
@@ -22,13 +22,14 @@ jobs:
           - stm32g474
           - stm32g483
           - stm32g484
-          #- stm32g491 # Does not seem ready yet
-          #- stm32g4a1 # Does not seem ready yet
+          - stm32g491 # Does not seem ready yet
+          - stm32g4a1 # Does not seem ready yet
         features:
           - log-rtt,defmt
           # TODO: -log-rtt # log-rtt without defmt, more combos?
           - log-itm
           - log-semihost
+          - cordic,log-rtt,defmt
 
     steps:
       - uses: actions/checkout@v2

Cargo.toml

@@ -13,7 +13,8 @@ version = "0.0.2"
 
 [dependencies]
 nb = "0.1.1"
-stm32g4 = "0.15.1"
+#stm32g4 = { git = "https://github.com/stm32-rs/stm32-rs-nightlies" } #"0.15.1"
+stm32g4 = { version = "0.19.0", package = "stm32g4-staging" }
 paste = "1.0"
 bitflags = "1.2"
 vcell = "0.1"

examples/adc-continious-dma.rs

@@ -10,7 +10,7 @@ use crate::hal::{
         AdcClaim, ClockSource, Temperature, Vref,
     },
     delay::SYSTDelayExt,
-    dma::{config::DmaConfig, stream::DMAExt, TransferExt},
+    dma::{channel::DMAExt, config::DmaConfig, TransferExt},
     gpio::GpioExt,
     pwr::PwrExt,
     rcc::{Config, RccExt},
@@ -36,7 +36,7 @@ fn main() -> ! {
     let pwr = dp.PWR.constrain().freeze();
     let mut rcc = rcc.freeze(Config::hsi(), pwr);
 
-    let streams = dp.DMA1.split(&rcc);
+    let channels = dp.DMA1.split(&rcc);
     let config = DmaConfig::default()
         .transfer_complete_interrupt(false)
         .circular_buffer(true)
@@ -62,7 +62,7 @@ fn main() -> ! {
 
     info!("Setup DMA");
     let first_buffer = cortex_m::singleton!(: [u16; 15] = [0; 15]).unwrap();
-    let mut transfer = streams.0.into_circ_peripheral_to_memory_transfer(
+    let mut transfer = channels.ch1.into_circ_peripheral_to_memory_transfer(
         adc.enable_dma(AdcDma::Continuous),
         &mut first_buffer[..],
         config,

examples/adc-one-shot-dma.rs

@@ -9,7 +9,7 @@ use crate::hal::{
         AdcClaim, ClockSource, Temperature,
     },
     delay::SYSTDelayExt,
-    dma::{config::DmaConfig, stream::DMAExt, TransferExt},
+    dma::{channel::DMAExt, config::DmaConfig, TransferExt},
     gpio::GpioExt,
     pwr::PwrExt,
     rcc::{Config, RccExt},
@@ -37,7 +37,7 @@ fn main() -> ! {
     let pwr = dp.PWR.constrain().freeze();
     let mut rcc = rcc.freeze(Config::hsi(), pwr);
 
-    let mut streams = dp.DMA1.split(&rcc);
+    let mut channels = dp.DMA1.split(&rcc);
     let config = DmaConfig::default()
         .transfer_complete_interrupt(false)
         .circular_buffer(false)
@@ -61,7 +61,7 @@ fn main() -> ! {
 
     info!("Setup DMA");
     let first_buffer = cortex_m::singleton!(: [u16; 2] = [0; 2]).unwrap();
-    let mut transfer = streams.0.into_peripheral_to_memory_transfer(
+    let mut transfer = channels.ch1.into_peripheral_to_memory_transfer(
         adc.enable_dma(AdcDma::Single),
         &mut first_buffer[..],
         config,
@@ -74,10 +74,10 @@ fn main() -> ! {
     info!("Conversion Done");
 
     transfer.pause(|adc| adc.cancel_conversion());
-    let (s0, adc, first_buffer) = transfer.free();
+    let (ch1, adc, first_buffer) = transfer.free();
     let adc = adc.disable();
 
-    streams.0 = s0;
+    channels.ch1 = ch1;
 
     let millivolts = adc.sample_to_millivolts(first_buffer[0]);
     info!("pa3: {}mV", millivolts);

examples/cordic.rs

@@ -7,11 +7,11 @@ extern crate cortex_m;
 extern crate cortex_m_rt as rt;
 extern crate stm32g4xx_hal as hal;
 
-use fixed::types::I1F15;
 use hal::cordic::{
-    func::{dynamic::Mode as _, scale::N0, Magnitude, SinCos, Sqrt},
+    op::{dynamic::Mode as _, Magnitude, SinCos, Sqrt},
     prec::P60,
-    types::{Q15, Q31},
+    scale::N0,
+    types::{I1F15, Q15, Q31},
     Ext as _,
 };
 use hal::prelude::*;
@@ -34,7 +34,7 @@ fn main() -> ! {
     let mut cordic = dp
         .CORDIC
         .constrain(&mut rcc)
-        .freeze::<Q15, Q31, SinCos, P60>(); // 16 bit arguments, 32 bit results, compute sine and cosine, 60 iterations
+        .freeze::<Q15, Q31, P60, SinCos>(); // 16 bit arguments, 32 bit results, compute sine and cosine, 60 iterations
 
     // static operation (zero overhead)
 
@@ -53,5 +53,6 @@ fn main() -> ! {
     let magnitude = cordic.run::<Magnitude>((I1F15::from_num(0.25), I1F15::from_num(0.5)));
     println!("magnitude: {}", magnitude.to_num::<f32>());
 
+    #[allow(clippy::empty_loop)]
     loop {}
 }

examples/flash_with_rtic.rs

@@ -73,7 +73,7 @@ mod app {
 
         unsafe {
             let mut flash = &(*stm32g4xx_hal::stm32::FLASH::ptr());
-            flash.acr.modify(|_, w| {
+            flash.acr().modify(|_, w| {
                 w.latency().bits(0b1000) // 8 wait states
             });
         }

examples/spi-dma.rs

@@ -22,8 +22,8 @@ use crate::hal::{
 
 use cortex_m_rt::entry;
 use stm32g4xx_hal as hal;
+use stm32g4xx_hal::dma::channel::DMAExt;
 use stm32g4xx_hal::dma::config::DmaConfig;
-use stm32g4xx_hal::dma::stream::DMAExt;
 use stm32g4xx_hal::dma::TransferExt;
 
 #[macro_use]
@@ -50,7 +50,7 @@ fn main() -> ! {
     let spi = dp
         .SPI1
         .spi((sclk, miso, mosi), spi::MODE_0, 400.kHz(), &mut rcc);
-    let streams = dp.DMA1.split(&rcc);
+    let channels = dp.DMA1.split(&rcc);
     let config = DmaConfig::default()
         .transfer_complete_interrupt(false)
         .circular_buffer(true)
@@ -62,10 +62,11 @@ fn main() -> ! {
         *item = index as u8;
     }
     let dma_buf = cortex_m::singleton!(: [u8; BUFFER_SIZE] = buf).unwrap();
-    let mut transfer_dma =
-        streams
-            .0
-            .into_memory_to_peripheral_transfer(spi.enable_tx_dma(), &mut dma_buf[..], config);
+    let mut transfer_dma = channels.ch1.into_memory_to_peripheral_transfer(
+        spi.enable_tx_dma(),
+        &mut dma_buf[..],
+        config,
+    );
     transfer_dma.start(|_spi| {});
     loop {
         delay_tim2.delay_ms(1000_u16);

examples/uart-dma-rx.rs

@@ -5,7 +5,7 @@
 
 extern crate cortex_m_rt as rt;
 
-use hal::dma::{config::DmaConfig, stream::DMAExt, TransferExt};
+use hal::dma::{channel::DMAExt, config::DmaConfig, TransferExt};
 use hal::prelude::*;
 use hal::pwr::PwrExt;
 use hal::serial::*;
@@ -30,7 +30,7 @@ fn main() -> ! {
     let pwr = dp.PWR.constrain().freeze();
     let mut rcc = rcc.freeze(rcc::Config::hsi(), pwr);
 
-    let streams = dp.DMA1.split(&rcc);
+    let channels = dp.DMA1.split(&rcc);
     let config = DmaConfig::default()
         .transfer_complete_interrupt(false)
         .circular_buffer(true)
@@ -65,7 +65,7 @@ fn main() -> ! {
 
     let (_tx, rx) = usart.split();
 
-    let mut transfer = streams.0.into_circ_peripheral_to_memory_transfer(
+    let mut transfer = channels.ch1.into_circ_peripheral_to_memory_transfer(
         rx.enable_dma(),
         &mut rx_buffer[..],
         config,

examples/uart-dma-tx.rs

@@ -7,7 +7,7 @@ extern crate cortex_m_rt as rt;
 
 use core::fmt::Write;
 
-use hal::dma::{config::DmaConfig, stream::DMAExt, TransferExt};
+use hal::dma::{channel::DMAExt, config::DmaConfig, TransferExt};
 use hal::prelude::*;
 use hal::pwr::PwrExt;
 use hal::serial::*;
@@ -32,7 +32,7 @@ fn main() -> ! {
     let pwr = dp.PWR.constrain().freeze();
     let mut rcc = rcc.freeze(rcc::Config::hsi(), pwr);
 
-    let streams = dp.DMA1.split(&rcc);
+    let channels = dp.DMA1.split(&rcc);
     let config = DmaConfig::default()
         .transfer_complete_interrupt(false)
         .circular_buffer(false)
@@ -64,10 +64,11 @@ fn main() -> ! {
     let (tx, _rx) = usart.split();
 
     // Setup DMA for USART2 TX with dma channel 1.
-    let mut transfer =
-        streams
-            .0
-            .into_memory_to_peripheral_transfer(tx.enable_dma(), &mut tx_buffer[..], config);
+    let mut transfer = channels.ch1.into_memory_to_peripheral_transfer(
+        tx.enable_dma(),
+        &mut tx_buffer[..],
+        config,
+    );
 
     transfer.start(|_tx| {});
     loop {