Allocate ACLINT register by 'SMP' configuration

Add an macro 'NUM_SMP' to device.h to indicate the number of SMPs, and
allocate the size of the array of the registers in ACLINT device with
the corresponding configuration.

Makefile

@@ -78,6 +78,7 @@ E :=
 S := $E $E
 
 SMP ?= 1
+CFLAGS += -DNUM_HARTS=$(SMP)
 .PHONY: riscv-harts.dtsi
 riscv-harts.dtsi:
 	$(Q)python3 scripts/gen-hart-dts.py $@ $(SMP) $(CLOCK_FREQ)

device.h

@@ -172,6 +172,12 @@ void virtio_blk_write(hart_t *vm,
 uint32_t *virtio_blk_init(virtio_blk_state_t *vblk, char *disk_file);
 #endif /* SEMU_HAS(VIRTIOBLK) */
 
+/* ACLINT */
+
+#ifndef NUM_HARTS
+#define NUM_HARTS 1
+#endif
+
 /* ACLINT MTIMER */
 typedef struct {
     /* A MTIMER device has two separate base addresses: one for the MTIME
@@ -190,7 +196,7 @@ typedef struct {
      * For more details, please refer to the register map at:
      * https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc#21-register-map
      */
-    uint64_t mtimecmp[4095];
+    uint64_t mtimecmp[NUM_HARTS];
     semu_timer_t mtime;
 } mtimer_state_t;
 
@@ -218,7 +224,7 @@ typedef struct {
      * For more details, please refer to the register map at:
      * https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc#31-register-map
      */
-    uint32_t msip[4096];
+    uint32_t msip[NUM_HARTS];
 } mswi_state_t;
 
 void aclint_mswi_update_interrupts(hart_t *hart, mswi_state_t *mswi);
@@ -245,7 +251,7 @@ typedef struct {
      * For more details, please refer to the register map at:
      * https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc#41-register-map
      */
-    uint32_t ssip[4096];
+    uint32_t ssip[NUM_HARTS];
 } sswi_state_t;
 
 void aclint_sswi_update_interrupts(hart_t *hart, sswi_state_t *sswi);