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WIP: ULX3S support#54

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osresearch wants to merge 28 commits intotinyfpga:mastertinyfpga/TinyFPGA-Bootloader:masterfrom osresearch:ulx3sosresearch/TinyFPGA-Bootloader:ulx3sCopy head branch name to clipboard

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Commits on Jan 18, 2019

• common: Make sure RAM inference works with yosys

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• common/serial: Fix syntax error

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• common: Make sure to always assign all 'reg's in processes to avoid latches

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• silence warnings

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• TinyFPGA_BX: enable some IO pins

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• TinyFPGA_BX: use clock crossing strobe to bridge the 48 MHz USB clock

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• usb_fs_rx: Document clock domains

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• Clock crossing success - endpoint runs at 12 Mhz

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• Clock crossing: cleanup uart debugging code

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• Clock crossing: cleanup uart debugging code and helpers

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• TinyFPGA_BX: enable all the pins, with -nowarn

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• TinyFPGA_BX: use nextpnr-ice40

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Commits on Jan 19, 2019

• test: generate 24 Mhz clk for tinyfpga_bootloader endpoint

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• usb: iverilog fixes for clock-crossing strobes

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Commits on May 28, 2019

• Merge branch 'master' into clock-crossing

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Commits on Jul 5, 2019

• ignore generated ecp5 files

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• usb_fs_rx: fix yosys error on dvalid

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• ulx3s: bootloader compiles, but does not yet enumerate on USB correctly

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• Merge remote-tracking branch 'osresearch/clock-crossing' into ulx3s

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• ulx3s: works with the clock-crossing USB driver

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• tinyprog: allow updates to the security pages

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• ulx3s: multi-boot image creation and SFDP security page json files

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• ulx3s: bootstrap flow

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• ignore generated ecp5 files

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• tinyprog: fix tab/whitespace issue

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Commits on Jul 6, 2019

• tinyprog: optimize re-writes by not erasing matching sectors or empty pages

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Commits on Aug 29, 2019

• ulx3s: flash target and updated documentation for write address

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• tinyprog: successful return code from security page write

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