Pinned Loading

1. MLPerf-Tiny-CFU_Accelerator MLPerf-Tiny-CFU_Accelerator Public

   Forked from nycu-caslab/AAML2024-project

   Implement 16x16 matrix computation using TPU and Systolic Array. IM2COL and filter flattening use 4-channel expansion to improve memory and computation efficiency.

   Verilog 1

2. Asynchronous_FIFO Asynchronous_FIFO Public

   Design an asynchronous FIFO to safely pass data from one clock domain to another asynchronous clock domain

   1

3. Round_Robin_Arbiter Round_Robin_Arbiter Public

   Design a round-robin arbiter to ensure that each request has an equal chance of being granted access to shared resources.

   SystemVerilog 1

4. Nbit_Bidirectional_Shift_Register Nbit_Bidirectional_Shift_Register Public

   Desig a bidirectional shift register with parameterized width

   Verilog 1

5. Parking_System_Moore_Machine Parking_System_Moore_Machine Public

   Design a parking system that can verify the password and control the gate when the entrance and exit sensors detect an approaching vehicle

   Verilog 1

6. Traffic_Light_Controller_Mealy_Machine Traffic_Light_Controller_Mealy_Machine Public

   Designing a traffic light controller to coordinate traffic lights on highways and farm ways

   Verilog 1