Add support for Xilinx Virtex-7 FPGA VC709 board #835

mbs0221 · 2021-03-25T13:08:29Z

Related issue:

Type of change: new feature

Impact: new fpga target

Release Notes

Add support for Xilinx Virtex-7 FPGA VC709 board.

Currently, the Linux kernel (version 5.11.0-rc3) can boot with the help of Open-SBI (version v0.9), and login with UART/Serial port on the Xilinx Virtex-7 FPGA VC709 board!

new file: src/main/resources/vc709/uartboot/Makefile new file: src/main/resources/vc709/uartboot/Makefile-back new file: src/main/resources/vc709/uartboot/common.h new file: src/main/resources/vc709/uartboot/crc16.c new file: src/main/resources/vc709/uartboot/crc16.o new file: src/main/resources/vc709/uartboot/gpoi.c new file: src/main/resources/vc709/uartboot/head.S new file: src/main/resources/vc709/uartboot/hello.c new file: src/main/resources/vc709/uartboot/include/bits.h new file: src/main/resources/vc709/uartboot/include/const.h new file: src/main/resources/vc709/uartboot/include/crc16.h new file: src/main/resources/vc709/uartboot/include/devices/clint.h new file: src/main/resources/vc709/uartboot/include/devices/gpio.h new file: src/main/resources/vc709/uartboot/include/devices/plic.h new file: src/main/resources/vc709/uartboot/include/devices/spi.h new file: src/main/resources/vc709/uartboot/include/devices/uart.h new file: src/main/resources/vc709/uartboot/include/kprintf.h new file: src/main/resources/vc709/uartboot/include/platform.h new file: src/main/resources/vc709/uartboot/include/riscv_test_defaults.h new file: src/main/resources/vc709/uartboot/include/sections.h new file: src/main/resources/vc709/uartboot/include/serial.h new file: src/main/resources/vc709/uartboot/include/smp.h new file: src/main/resources/vc709/uartboot/kprintf.c new file: src/main/resources/vc709/uartboot/linker/bootrom.elf.lds new file: src/main/resources/vc709/uartboot/linker/memory.lds new file: src/main/resources/vc709/uartboot/plic.c new file: src/main/resources/vc709/uartboot/sd.c new file: src/main/resources/vc709/uartboot/serial.c new file: src/main/resources/vc709/uartboot/uart.c new file: src/main/resources/vc709/uartsend/Makefile new file: src/main/resources/vc709/uartsend/serial new file: src/main/resources/vc709/uartsend/serial.c new file: src/main/resources/vc709/uartsend/serial.o new file: src/main/scala/vc709/Configs.scala new file: src/main/scala/vc709/CustomOverlays.scala new file: src/main/scala/vc709/TestHarness.scala modified: Makefile

modified: fpga/src/main/scala/vc709/Configs.scala modified: fpga/src/main/scala/vc709/TestHarness.scala modified: fpga/fpga-shells (new commits, modified content) modified: generators/rocket-chip (new commits)

modified: src/main/resources/vc709/uartboot/head.S modified: src/main/resources/vc709/uartboot/linker/bootrom.elf.lds modified: src/main/resources/vc709/uartboot/linker/memory.lds modified: src/main/scala/vc709/Configs.scala modified: src/main/scala/vc709/CustomOverlays.scala modified: src/main/scala/vc709/TestHarness.scala

modified: src/main/scala/vc709/Configs.scala modified: src/main/scala/vc709/CustomOverlays.scala new file: src/main/scala/vc709/HarnessBinders.scala modified: src/main/scala/vc709/TestHarness.scala modified: Makefile deleted: src/main/resources/vc709/uartboot/crc16.o modified: src/main/resources/vc709/uartboot/head.S modified: src/main/resources/vc709/uartboot/linker/bootrom.elf.lds modified: src/main/resources/vc709/uartboot/linker/memory.lds

abejgonzalez · 2021-03-28T21:32:36Z

fpga/Makefile

 #########################################################################################
 # general cleanup rules
 #########################################################################################
 .PHONY: clean
 clean:
-	rm -rf $(gen_dir)


In Chipyard we have this clean target "clean" everything (hence the gen_dir being deleted). I wouldn't be opposed to adding a new target like clean-specific (or a better name) that just deletes the sources related to this config.

So I would revert this.

I agree with your suggestion that It would be better to have a new target like clean-specific for a certain config!

abejgonzalez · 2021-03-28T21:33:32Z

fpga/Makefile

@@ -71,6 +85,7 @@ default: $(mcs)
 # misc. directories
 #########################################################################################
 fpga_dir := $(base_dir)/fpga/fpga-shells/$(FPGA_BRAND)
+fpga_board_script_dir := $(fpga_dir)/$(BOARD)/tcl


Where is this used?

It is originally used in sifive/freedom. I do not remember the original intention. It can be removed since we no longer need it currently.

abejgonzalez · 2021-03-28T21:34:27Z

fpga/Makefile

@@ -120,9 +135,19 @@ debug-bitstream: $(build_dir)/obj/post_synth.dcp
 			$(build_dir)/debug_obj \
 			$(fpga_common_script_dir)

+MCS_FILE := $(build_dir)/obj/$(MODEL).mcs


What is the MCS file used for? I removed this when originally setting up this work to keep things clean.

Since every time we power off the board, the uploaded bit-stream will be lost. When working around the kernel after building up the prototype, we would not want to upload the bit-stream too often. Having a mcs file is better choice. It will save our time in the post stage of testing the prototype!

abejgonzalez · 2021-03-28T21:35:21Z

fpga/src/main/resources/vc709/uartboot/gpoi.c

@@ -0,0 +1,9 @@
+/*


Mis-spelled filename gpoi -> gpio.

It is a mistake to be corrected.

abejgonzalez · 2021-03-28T21:39:23Z

fpga/README.md

@@ -0,0 +1,50 @@
+# Guide


2 points here. 1st. We are currently trying to get FireMarshal to target the prototype platforms so a lot involving building Linux won't be necessary (stay tuned for that). 2nd. At a minimum, this should be put in markdown and put in the Chipyard docs in the prototyping section. Once that is done we can talk more about how to make this a bit more understandable for folks.

abejgonzalez · 2021-03-28T21:45:50Z

First of all, thanks for the contribution! I gave a quick 1st pass on the PR.

May you change the target to the dev branch. We use that branch for development work.

As mentioned in this post: #784 (comment)... we are still trying to figure out some testing infrastructure since it's hard to test this stuff when we don't have the boards to run regressions. I'll let you know what the status is on that since that is a bit slow right now.

WithTLBackingMemory is moved to the front of WithSystemModifications so that the size of ExtMem is updated and in effect.

…vc709-dev

update MEMORY_MEM_SIZE

mbs0221 added 23 commits February 1, 2021 18:18

update support for vc709

7888b11

add support for vc709

98bb00f

modified: fpga/src/main/scala/vc709/Configs.scala modified: fpga/src/main/scala/vc709/TestHarness.scala modified: fpga/fpga-shells (new commits, modified content) modified: generators/rocket-chip (new commits)

update support for vc709

e6f4528

support DDR3 dual memory channels for vc709

a09bb6f

update support for dual memory channels

18c2da2

support PCIeX8 for vc709

83e6b65

update PCIeX8 support for vc709

82b20a8

update support for dual memory channels and PCIe X8

44e91e5

update Makefile

550628a

update Makefile of uartsend

498b978

update support for vc709 board

5134387

update support for vc709

33e001a

add README.md

4554b85

update Configs.scala

c6a02ef

update I2C and PCIe support for vc709 board.

de74a18

remove unnecessary files

36c7d1e

update support for I2C, UART and PCIe.

26fce71

update support for one DDR3 controller

8ea6d38

updata support for GPIO in vc709

0959757

update support for vc709 board

52f5f3d

mbs0221 changed the title ~~vc709 dev~~ Add support for Xilinx Virtex-7 FPGA VC709 board Mar 25, 2021

mbs0221 mentioned this pull request Mar 25, 2021

Add support for Xilinx Virtex-7 FPGA VC709 board sifive/fpga-shells#160

Open

abejgonzalez reviewed Mar 28, 2021

View reviewed changes

mbs0221 changed the base branch from master to dev March 29, 2021 05:14

mbs0221 added 2 commits March 29, 2021 13:38

Update and rename gpoi.c to gpio.c

d97e5d7

Update Configs.scala

49db3be

WithTLBackingMemory is moved to the front of WithSystemModifications so that the size of ExtMem is updated and in effect.

mbs0221 requested a review from abejgonzalez March 29, 2021 06:24

mbs0221 added 3 commits March 31, 2021 20:34

update UART support for vc709

a5e2c13

Merge branch 'vc709-dev' of https://github.com/mbs0221/chipyard into …

310e81b

…vc709-dev

Update platform.h

d26e1c3

update MEMORY_MEM_SIZE

mbs0221 closed this May 5, 2021

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Add support for Xilinx Virtex-7 FPGA VC709 board #835

Add support for Xilinx Virtex-7 FPGA VC709 board #835

mbs0221 commented Mar 25, 2021 •

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abejgonzalez commented Mar 28, 2021

Add support for Xilinx Virtex-7 FPGA VC709 board #835

Add support for Xilinx Virtex-7 FPGA VC709 board #835

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abejgonzalez commented Mar 28, 2021

mbs0221 commented Mar 25, 2021 •

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