Implement our own TLB

src/main/scala/dmem/DCache.scala

@@ -15,7 +15,7 @@ import freechips.rocketchip.rocket._
 case class ShuttleDCacheParams(
   nSets: Int = 64,
   nWays: Int = 4,
-  nMSHRs: Int = 8,
+  nMSHRs: Int = 4,
   nBanks: Int = 4,
   nTagBanks: Int = 4,
   singlePorted: Boolean = true,
@@ -173,7 +173,7 @@ class ShuttleDCacheModule(outer: ShuttleDCache) extends LazyModuleImp(outer)
   val s1_replay_read  = isRead(s1_replay_req.cmd)
   val s1_replay_write = isWrite(s1_replay_req.cmd)
   val s1_replay_readwrite = s1_replay_read || s1_replay_write || isPrefetch(s1_replay_req.cmd)
-  
+
   // check for unsupported operations
   assert(!s1_valid || !s1_req.cmd.isOneOf(M_PWR))
 
@@ -186,9 +186,6 @@ class ShuttleDCacheModule(outer: ShuttleDCache) extends LazyModuleImp(outer)
   when (s1_valid) {
     s2_req.addr := s1_addr
   }
-  when (s1_replay_valid && s1_replay_write) {
-    s2_replay_req.data := mshrs.io.replay.bits.data
-  }
 
   // tags
   def onReset = L1Metadata(0.U, ClientMetadata.onReset)

src/main/scala/dmem/MSHRs.scala

@@ -150,8 +150,8 @@ class ShuttleDCacheMSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends L1H
   io.refill := refillMux(io.mem_grant.bits.source)
 
   val free_sdq = io.replay.fire() && isWrite(io.replay.bits.cmd)
-  io.replay.bits.data := sdq(RegEnable(replay_arb.io.out.bits.sdq_id, free_sdq)).data
-  io.replay.bits.mask := sdq(RegEnable(replay_arb.io.out.bits.sdq_id, free_sdq)).mask
+  io.replay.bits.data := sdq(replay_arb.io.out.bits.sdq_id).data
+  io.replay.bits.mask := sdq(replay_arb.io.out.bits.sdq_id).mask
   io.replay_way := Mux1H(UIntToOH(replay_arb.io.chosen), mshrs.map(_.io.meta_write.bits.way_en))
   io.replay.valid := replay_arb.io.out.valid
   io.replay.bits := replay_arb.io.out.bits

src/main/scala/dmem/PMA.scala

@@ -0,0 +1,48 @@
+package shuttle.dmem
+
+import chisel3._
+import chisel3.util._
+
+import org.chipsalliance.cde.config.{Field, Parameters}
+import freechips.rocketchip.subsystem.CacheBlockBytes
+import freechips.rocketchip.diplomacy.RegionType
+import freechips.rocketchip.tile.{CoreModule, CoreBundle}
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.rocket._
+import freechips.rocketchip.util._
+import freechips.rocketchip.util.property
+import freechips.rocketchip.devices.debug.DebugModuleKey
+import chisel3.experimental.SourceInfo
+
+class PMAChecker(edge: TLEdgeOut)(implicit p: Parameters) extends CoreModule()(p) {
+  val io = IO(new Bundle {
+    val paddr = Input(UInt())
+
+    val resp = Output(new Bundle {
+      val cacheable = Bool()
+      val r = Bool()
+      val w = Bool()
+      val pp = Bool()
+      val al = Bool()
+      val aa = Bool()
+      val x = Bool()
+      val eff = Bool()
+    })
+  })
+
+  // PMA
+  // check exist a slave can consume this address.
+  val legal_address = edge.manager.findSafe(io.paddr).reduce(_||_)
+  // check utility to help check SoC property.
+  def fastCheck(member: TLManagerParameters => Boolean) =
+    legal_address && edge.manager.fastProperty(io.paddr, member, (b:Boolean) => b.B)
+
+  io.resp.cacheable := fastCheck(_.supportsAcquireB)
+  io.resp.r := fastCheck(_.supportsGet)
+  io.resp.w := fastCheck(_.supportsPutFull)
+  io.resp.pp := fastCheck(_.supportsPutPartial)
+  io.resp.al := fastCheck(_.supportsLogical)
+  io.resp.aa := fastCheck(_.supportsArithmetic)
+  io.resp.x := fastCheck(_.executable)
+  io.resp.eff := fastCheck(Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains _.regionType)
+}