Add default constructors to registers.

crates/ads126x/src/register.rs

@@ -76,6 +76,37 @@ bitflags! {
     }
 }
 
+impl PowerRegister {
+    pub fn default() -> Self {
+        PowerRegister::from_bits_truncate(0b0001_0001)
+    }
+
+    pub fn set_vbias(&mut self, vbias: bool) {
+        if vbias {
+            self.insert(PowerRegister::VBIAS);
+        } else {
+            self.remove(PowerRegister::VBIAS);
+        }
+    }
+
+    pub fn set_intref(&mut self, intref: bool) {
+        if intref {
+            self.insert(PowerRegister::INTREF);
+        } else {
+            self.remove(PowerRegister::INTREF);
+        }
+    }
+
+    pub fn get_reset(&self) -> bool {
+        self.contains(PowerRegister::RESET)
+    }
+
+    // must be cleared if set to detect further resets. 
+    pub fn clear_reset(&mut self) {
+        self.remove(PowerRegister::RESET);
+    }
+}
+
 bitflags! {
     /// WARNING: If CRC is 0b11 set by ADC, it will reflect as CRC enabled not reserved.
     /// CRC only accounts for 0b00 disabled and 0b01 enabled.
@@ -86,6 +117,50 @@ bitflags! {
     }
 }
 
+impl InterfaceRegister {
+    pub fn default() -> Self {
+        InterfaceRegister::from_bits_truncate(0b0000_0101)
+    }
+
+    pub fn get_crc(&self) -> CrcMode {
+        match self.bits() & 0b0000_0001 {
+            0b00 => CrcMode::Disabled,
+            0b01 => CrcMode::Checksum,
+            0b10 => CrcMode::CRC,
+            _ => unreachable!(),
+        }
+    }
+
+    pub fn set_crc(&mut self, crc: CrcMode) {
+        let bits = crc as u8;
+        self.insert(InterfaceRegister::from_bits_retain(bits));
+    }
+
+    pub fn get_status(&self) -> bool {
+        self.contains(InterfaceRegister::STATUS)
+    }
+
+    pub fn set_status(&mut self, status: bool) {
+        if status {
+            self.insert(InterfaceRegister::STATUS);
+        } else {
+            self.remove(InterfaceRegister::STATUS);
+        }
+    }
+
+    pub fn get_timeout(&self) -> bool {
+        self.contains(InterfaceRegister::TIMEOUT)
+    }
+
+    pub fn set_timeout(&mut self, timeout: bool) {
+        if timeout {
+            self.insert(InterfaceRegister::TIMEOUT);
+        } else {
+            self.remove(InterfaceRegister::TIMEOUT);
+        }
+    }
+}
+
 bitflags! {
     pub struct Mode0Register: u8 {
         const RUNMODE = 0b0100_0000;
@@ -96,6 +171,10 @@ bitflags! {
 }
 
 impl Mode0Register {
+    pub fn default() -> Self {
+        Mode0Register::from_bits_truncate(0b0000_0000)
+    }
+
     pub fn get_delay(&self) -> ConversionDelay {
         match self.bits() & 0b0000_1111 {
             0b0000 => ConversionDelay::DNone,
@@ -148,6 +227,10 @@ bitflags! {
 }
 
 impl Mode1Register {
+    pub fn default() -> Self {
+        Mode1Register::from_bits_truncate(0b1000_0000)
+    }
+
     pub fn get_sbmag(&self) -> SensorBiasMagnitude {
         match self.bits() & 0b0000_0111 {
             0b000 => SensorBiasMagnitude::BNone,
@@ -255,6 +338,10 @@ bitflags! {
 }
 
 impl InpMuxRegister {
+    pub fn default() -> Self {
+        InpMuxRegister::from_bits_truncate(0b0000_0001)
+    }
+
     pub fn get_muxn(&self) -> NegativeInpMux {
         match self.bits() & 0b0000_1111 {
             0b0000 => NegativeInpMux::AIN0,
@@ -319,6 +406,10 @@ bitflags! {
 }
 
 impl IdacMuxRegister {
+    pub fn default() -> Self {
+        IdacMuxRegister::from_bits_truncate(0b1011_1011)
+    }
+
     pub fn get_mux1(&self) -> IdacOutMux {
         match self.bits() & 0b0000_1111 {
             0b0000 => IdacOutMux::AIN0,
@@ -377,6 +468,10 @@ bitflags! {
 }
 
 impl IdacMagRegister {
+    pub fn default() -> Self {
+        IdacMagRegister::from_bits_truncate(0b0000_0000)
+    }
+
     pub fn get_mag1(&self) -> IdacCurMag {
         match self.bits() & 0b0000_1111 {
             0b0000 => IdacCurMag::I50uA,
@@ -431,6 +526,10 @@ bitflags! {
 }
 
 impl RefMuxRegister {
+    pub fn default() -> Self {
+        RefMuxRegister::from_bits_truncate(0b0000_0000)
+    }
+
     pub fn get_rmuxn(&self) -> RefNegativeInp {
         match self.bits() & 0b0000_0111 {
             0b000 => RefNegativeInp::Int2_5VRef,
@@ -477,6 +576,11 @@ bitflags! {
 }
 
 impl TdacpRegister {
+    // there is no defined default values in the datasheet so just zeros. 
+    pub fn default() -> Self {
+        TdacpRegister::from_bits_truncate(0b0000_0000)
+    }
+
     pub fn get_magp(&self) -> TdacOutMag {
         match self.bits() & 0b0001_1111 {
             0b01001 => TdacOutMag::V4_5,
@@ -519,6 +623,11 @@ bitflags! {
 }
 
 impl TdacnRegister {
+    // there is no defined default values in the datasheet so just zeros. 
+    pub fn default() -> Self {
+        TdacnRegister::from_bits_truncate(0b0000_0000)
+    }
+
     pub fn get_magn(&self) -> TdacOutMag {
         match self.bits() & 0b0001_1111 {
             0b01001 => TdacOutMag::V4_5,
@@ -565,6 +674,12 @@ bitflags! {
     }
 }
 
+impl GpioConRegister {
+    pub fn default() -> Self {
+        GpioConRegister::from_bits_truncate(0b0000_0000)
+    }
+}
+
 bitflags! {
     /// Setting `DIR<x>` to:
     /// - 0 = `GPIO<x>` is output
@@ -581,6 +696,12 @@ bitflags! {
     }
 }
 
+impl GpioDirRegister {
+    pub fn default() -> Self {
+        GpioDirRegister::from_bits_truncate(0b0000_0000)
+    }
+}
+
 bitflags! {
     /// If `GPIO<x>` is output, read returns 0b.
     /// If `GPIO<x>` is input, write sets `GPIO<x>` to high (if 1) or low (if 0).
@@ -596,13 +717,24 @@ bitflags! {
     }
 }
 
+impl GpioDatRegister {
+    // there is no defined default values in the datasheet so just zeros. 
+    pub fn default() -> Self {
+        GpioDatRegister::from_bits_truncate(0b0000_0000)
+    }
+}
+
 bitflags! {
     pub struct Adc2CfgRegister: u8 {
         const _ = !0; // Source may set any bits
     }
 }
 
 impl Adc2CfgRegister {
+    pub fn default() -> Self {
+        Adc2CfgRegister::from_bits_truncate(0b0000_0000)
+    }
+
     pub fn get_gain2(&self) -> Adc2Gain {
         match self.bits() & 0b0000_0111 {
             0b000 => Adc2Gain::VV1,
@@ -665,6 +797,10 @@ bitflags! {
 }
 
 impl Adc2MuxRegister {
+    pub fn default() -> Self {
+        Adc2MuxRegister::from_bits_truncate(0b0000_0001)
+    }
+
     pub fn get_muxn2(&self) -> NegativeInpMux {
         match self.bits() & 0b0000_1111 {
             0b0000 => NegativeInpMux::AIN0,

crates/ads126x/src/register/enums.rs

@@ -68,6 +68,13 @@ pub enum SensorBiasMagnitude {
     R10MOhm = 0b110,
 }
 
+#[repr(u8)]
+pub enum CrcMode {
+    Disabled = 0b00,
+    Checksum = 0b01,
+    CRC = 0b10, 
+}
+
 #[repr(u8)]
 pub enum DigitalFilter {
     Sinc1 = 0b000,