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* Add adc crate init. * WIP: Init driver * Convert RREG and WREG to use Register not u8 * Added getters and setters for ID, POWER, and INTERFACE registers * Rename read_register to read_multiple_registers. Remove call to read_multiple_registers for a single register call. * Update doc * Converted WREG to single and multiple variant * Added set_crc and removed RESERVED from Crc enum * Convert CRC from enum to bitflag * Moved status register to register module * Added MODE register impls * Added more registers * Removed redundant StatusRegister impl block * Added more registers * Implemented last registers * Align Register values * Start init and add default example to Mode2Register. * Add default constructors to registers. * Rework driver to avoid taking ownership of spi peripheral. * Change path to git path for HAL import. * Create temperature board adc manager. * Add ADC manager to all boards. --------- Co-authored-by: Bradley Myers <[email protected]>
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Original file line number | Diff line number | Diff line change |
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use ads126x::{ | ||
register::{DataRate, Mode1Register, Mode2Register}, | ||
ADCCommand, Ads126x, | ||
}; | ||
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use common_arm::spawn; | ||
use stm32h7xx_hal::{ | ||
gpio::{Output, Pin, PushPull}, | ||
spi::Spi, | ||
}; | ||
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use crate::app::delay; | ||
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// There is an option to use interrupts using the data ready pins, but for now we will poll. | ||
pub struct AdcManager { | ||
pub spi: Spi<stm32h7xx_hal::pac::SPI4, stm32h7xx_hal::spi::Enabled, u8>, | ||
pub adc1: Ads126x<Pin<'C', 11, Output<PushPull>>>, | ||
pub adc2: Ads126x<Pin<'E', 0, Output<PushPull>>>, | ||
pub adc1_cs: Pin<'C', 10, Output<PushPull>>, | ||
pub adc2_cs: Pin<'D', 2, Output<PushPull>>, | ||
} | ||
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impl AdcManager { | ||
pub fn new( | ||
spi: Spi<stm32h7xx_hal::pac::SPI4, stm32h7xx_hal::spi::Enabled, u8>, | ||
adc1_rst: Pin<'C', 11, Output<PushPull>>, | ||
adc2_rst: Pin<'E', 0, Output<PushPull>>, | ||
adc1_cs: Pin<'C', 10, Output<PushPull>>, | ||
adc2_cs: Pin<'D', 2, Output<PushPull>>, | ||
) -> Self { | ||
Self { | ||
spi, | ||
adc1: Ads126x::new(adc1_rst), | ||
adc2: Ads126x::new(adc2_rst), | ||
adc1_cs, | ||
adc2_cs, | ||
} | ||
} | ||
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pub fn init_adc1(&mut self) -> Result<(), ads126x::error::ADS126xError> { | ||
self.adc2_cs.set_high(); | ||
self.adc1_cs.set_low(); | ||
self.adc1.reset()?; | ||
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spawn!(delay, 1000); | ||
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let mut mode1_cfg = Mode1Register::default(); | ||
mode1_cfg.set_filter(ads126x::register::DigitalFilter::Sinc1); | ||
self.adc1.set_mode1(&mode1_cfg, &mut self.spi)?; | ||
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let mut mode2_cfg = Mode2Register::default(); | ||
mode2_cfg.set_dr(DataRate::SPS1200); | ||
self.adc1.set_mode2(&mode2_cfg, &mut self.spi)?; | ||
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self.adc1.send_command(ADCCommand::START1, &mut self.spi)?; | ||
self.adc1.send_command(ADCCommand::START2, &mut self.spi)?; | ||
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Ok(()) | ||
} | ||
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pub fn init_adc2(&mut self) -> Result<(), ads126x::error::ADS126xError> { | ||
self.adc1_cs.set_high(); | ||
self.adc2_cs.set_low(); | ||
self.adc2.reset()?; | ||
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spawn!(delay, 1000); | ||
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let mut mode1_cfg = Mode1Register::default(); | ||
mode1_cfg.set_filter(ads126x::register::DigitalFilter::Sinc1); | ||
self.adc1.set_mode1(&mode1_cfg, &mut self.spi)?; | ||
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let mut mode2_cfg = Mode2Register::default(); | ||
mode2_cfg.set_dr(DataRate::SPS1200); | ||
self.adc1.set_mode2(&mode2_cfg, &mut self.spi)?; | ||
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self.adc1.send_command(ADCCommand::START1, &mut self.spi)?; | ||
self.adc1.send_command(ADCCommand::START2, &mut self.spi)?; | ||
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Ok(()) | ||
} | ||
} |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,81 @@ | ||
use ads126x::{ | ||
register::{DataRate, Mode1Register, Mode2Register}, | ||
ADCCommand, Ads126x, | ||
}; | ||
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use common_arm::spawn; | ||
use stm32h7xx_hal::{ | ||
gpio::{Output, Pin, PushPull}, | ||
spi::Spi, | ||
}; | ||
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use crate::app::delay; | ||
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// There is an option to use interrupts using the data ready pins, but for now we will poll. | ||
pub struct AdcManager { | ||
pub spi: Spi<stm32h7xx_hal::pac::SPI4, stm32h7xx_hal::spi::Enabled, u8>, | ||
pub adc1: Ads126x<Pin<'C', 11, Output<PushPull>>>, | ||
pub adc2: Ads126x<Pin<'E', 0, Output<PushPull>>>, | ||
pub adc1_cs: Pin<'C', 10, Output<PushPull>>, | ||
pub adc2_cs: Pin<'D', 2, Output<PushPull>>, | ||
} | ||
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impl AdcManager { | ||
pub fn new( | ||
spi: Spi<stm32h7xx_hal::pac::SPI4, stm32h7xx_hal::spi::Enabled, u8>, | ||
adc1_rst: Pin<'C', 11, Output<PushPull>>, | ||
adc2_rst: Pin<'E', 0, Output<PushPull>>, | ||
adc1_cs: Pin<'C', 10, Output<PushPull>>, | ||
adc2_cs: Pin<'D', 2, Output<PushPull>>, | ||
) -> Self { | ||
Self { | ||
spi, | ||
adc1: Ads126x::new(adc1_rst), | ||
adc2: Ads126x::new(adc2_rst), | ||
adc1_cs, | ||
adc2_cs, | ||
} | ||
} | ||
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pub fn init_adc1(&mut self) -> Result<(), ads126x::error::ADS126xError> { | ||
self.adc2_cs.set_high(); | ||
self.adc1_cs.set_low(); | ||
self.adc1.reset()?; | ||
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spawn!(delay, 1000); | ||
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let mut mode1_cfg = Mode1Register::default(); | ||
mode1_cfg.set_filter(ads126x::register::DigitalFilter::Sinc1); | ||
self.adc1.set_mode1(&mode1_cfg, &mut self.spi)?; | ||
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let mut mode2_cfg = Mode2Register::default(); | ||
mode2_cfg.set_dr(DataRate::SPS1200); | ||
self.adc1.set_mode2(&mode2_cfg, &mut self.spi)?; | ||
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self.adc1.send_command(ADCCommand::START1, &mut self.spi)?; | ||
self.adc1.send_command(ADCCommand::START2, &mut self.spi)?; | ||
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Ok(()) | ||
} | ||
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pub fn init_adc2(&mut self) -> Result<(), ads126x::error::ADS126xError> { | ||
self.adc1_cs.set_high(); | ||
self.adc2_cs.set_low(); | ||
self.adc2.reset()?; | ||
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spawn!(delay, 1000); | ||
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let mut mode1_cfg = Mode1Register::default(); | ||
mode1_cfg.set_filter(ads126x::register::DigitalFilter::Sinc1); | ||
self.adc1.set_mode1(&mode1_cfg, &mut self.spi)?; | ||
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let mut mode2_cfg = Mode2Register::default(); | ||
mode2_cfg.set_dr(DataRate::SPS1200); | ||
self.adc1.set_mode2(&mode2_cfg, &mut self.spi)?; | ||
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self.adc1.send_command(ADCCommand::START1, &mut self.spi)?; | ||
self.adc1.send_command(ADCCommand::START2, &mut self.spi)?; | ||
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Ok(()) | ||
} | ||
} |
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