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Adc driver #7

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Dec 14, 2024
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2 changes: 1 addition & 1 deletion crates/ads126x/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -9,12 +9,12 @@ embedded-hal = {workspace = true}
bitflags = { version = "2.3.1", features = ["serde"] }
nb = "1.1.0"
heapless = {workspace = true}
cortex-m = { workspace = true }

[dev-dependencies]
defmt-test = { workspace = true }
panic-probe = { workspace = true }
stm32h7xx-hal = { workspace = true }
cortex-m = { workspace = true }

[[test]]
name = "example"
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46 changes: 42 additions & 4 deletions crates/ads126x/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -10,16 +10,19 @@ use register::{
};

use embedded_hal::spi::FullDuplex;
use embedded_hal::digital::v2::OutputPin;
use heapless::Vec;

/// The [`Result`] type for ADS126x operations.
pub type Result<T> = core::result::Result<T, ADS126xError>;

pub struct ADS126x<SPI>
pub struct ADS126x<SPI, GpioPin>
where
SPI: FullDuplex<u8>,
GpioPin: OutputPin<Error = ()>,
{
spi: SPI,
reset_pin: GpioPin,
}

pub enum ADCCommand {
Expand All @@ -41,12 +44,47 @@ pub enum ADCCommand {
WREG(Register, u8), // (register address, number of registers)
}

impl<SPI> ADS126x<SPI>
fn delay(delay: u32) {
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This is added since normally one would call a Delay object from the HAL that is clocked by SysTick to delay when needed, but RTIC consumes SysTick. Not feasible (IMO) to propagate RTIC delays down to this level. Possible that an implementation of Delay could be created with a clock object instead of SysTick but I haven't look into this in depth.

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Is delay in μs, and is nop guaranteed to take precisely 1 clock cycle? If nop takes 1 clock cycle, then we'd need to go 0..(delay * cycles/delay_unit_of_time) no?

for _ in 0..delay {
cortex_m::asm::nop();
}
}

impl<SPI, GpioPin> ADS126x<SPI, GpioPin>
where
SPI: FullDuplex<u8>,
GpioPin: OutputPin<Error = ()>,
{
pub fn new(spi: SPI) -> Self {
Self { spi }
pub fn new(spi: SPI, reset_pin: GpioPin) -> Self {
Self { spi, reset_pin }
}

pub fn init(&mut self) -> Result<()> {
self.reset()?;
// write configuration registers
delay(65536); // must wait 2^16 clock cycles, is this SPI clock?
let mut mode2_cfg = Mode2Register::default();
mode2_cfg.set_dr(register::DataRate::SPS1200);
self.set_mode2(&mode2_cfg)?;

// Set the rest of the registers below
// ...

// start adc1
self.send_command(ADCCommand::START1)?;
// start adc2
self.send_command(ADCCommand::START2)?;
Ok(())
}

fn reset(&mut self) -> Result<()> {
self.reset_pin.set_high().map_err(|_| ADS126xError::IO)?;
delay(1000);
self.reset_pin.set_low().map_err(|_| ADS126xError::IO)?;
delay(1000);
self.reset_pin.set_high().map_err(|_| ADS126xError::IO)?;
delay(1000);
Ok(())
}

pub fn send_command(&mut self, command: ADCCommand) -> Result<()> {
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4 changes: 4 additions & 0 deletions crates/ads126x/src/register.rs
Original file line number Diff line number Diff line change
Expand Up @@ -196,6 +196,10 @@ bitflags! {
}

impl Mode2Register {
pub fn default() -> Self {
Mode2Register::from_bits_truncate(0b0000_0100)
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}

pub fn get_dr(&self) -> DataRate {
match self.bits() & 0b0000_1111 {
0b0000 => DataRate::SPS2_5,
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