Adding Number of Logic levels and number of timing graph levels to ti…#2383

Open

behnam-rs wants to merge 2 commits intoverilog-to-routing:openfpgafrom behnam-rs:Logic_levelizer

+185-20

Commits on Aug 31, 2023

Adding Number of Logic levels and number of timing graph levels to timing setup and hold reports
miladeb8
committed
Adding Number of Logic levels and number of timing graph levels to timing setup and hold reports
miladeb8
committed