radeonsi: don't use SET_SH_REG_INDEX on gfx7-9

It was accidentally used with geometry shaders. It might have caused hangs. Fixes: ccaaf8f - amd: massively simplify how info->spi_cu_en is applied Reviewed-by: Qiang Yu <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833> (cherry picked from commit d98501f)
waydroid · Jun 7, 2023 · 8c92afe · 8c92afe
1 parent 4224ef0
commit 8c92afe
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Showing 2 changed files with 8 additions and 3 deletions.
diff --git a/.pick_status.json b/.pick_status.json
@@ -589,7 +589,7 @@
         "description": "radeonsi: don't use SET_SH_REG_INDEX on gfx7-9",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": "ccaaf8fe04c956d9f16f98b7f7fa69a2526283bc"
     },

diff --git a/src/gallium/drivers/radeonsi/si_build_pm4.h b/src/gallium/drivers/radeonsi/si_build_pm4.h
@@ -128,8 +128,13 @@
 #define radeon_set_sh_reg_idx3_seq(sctx, reg, num) do { \
    SI_CHECK_SHADOWED_REGS(reg, num); \
    assert((reg) >= SI_SH_REG_OFFSET && (reg) < SI_SH_REG_END); \
-   radeon_emit(PKT3(PKT3_SET_SH_REG_INDEX, num, 0)); \
-   radeon_emit((((reg) - SI_SH_REG_OFFSET) >> 2) | ((sctx)->gfx_level >= GFX10 ? 3 << 28 : 0)); \
+   if ((sctx)->gfx_level >= GFX10) { \
+      radeon_emit(PKT3(PKT3_SET_SH_REG_INDEX, num, 0)); \
+      radeon_emit((((reg) - SI_SH_REG_OFFSET) >> 2) | (3 << 28)); \
+   } else { \
+      radeon_emit(PKT3(PKT3_SET_SH_REG, num, 0)); \
+      radeon_emit(((reg) - SI_SH_REG_OFFSET) >> 2); \
+   } \
 } while (0)
 
 #define radeon_set_sh_reg(reg, value) do { \