doc: update various readmes

README.md

@@ -18,24 +18,28 @@ The main system architecture is designed as follows (outdated):
 
 ![Architecture](https://cdn.hackaday.io/images/6958041523363605244.jpg)
 
-There are three major parts needs to be implemented: the Game Boy CPU (8-bit CISC Processor called SM83, Intel 8080 like), the PPU (Pixel Processing Unit), and the sound unit. Several interfacing modules are needed to support the IO capability provided by the specific hardware (FPGA development board or "VerilogBoy Handheld").
+There are three major parts needs to be implemented: the Game Boy CPU (8-bit CISC Processor called SM83, Intel 8080 like), the PPU (Pixel Processing Unit), and the sound unit (sometimes referred as a PSG, Programmable Sound Generator). Several interfacing modules are needed to support the IO capability provided by the specific hardware (FPGA development board or "VerilogBoy Handheld").
 
 ## Targets (Ports)
 
 Current Pano Logic G1 is the only supported platform. ML505 and VBH support are planned. 
 
 ## Progress
 
-![Running-on-ML505](https://cdn.hackaday.io/images/8583531548721704232.jpg)
-
-Refactoring in progress. Previous version could run *The Legend of Zelda: Link's Awakening* and *Pokemon Yellow* with no noticable glitch on the Xilinx ML505 board (as shown in the photo). See 'master' branch for previous version, at least for now.
+Refactoring in progress. Current version could run several commerical games with no noticable glitch on the Pano Logic G1 device. 'Master' branch contains the previous version that runs on the ML505.
 
  - [x] SM83 CPU (Refactoring stage 1 done, passes all Blargg's tests)
  - [x] PPU (Pixel Processing Unit, Pixel-FIFO architecture)
  - [x] OAMDMA (Object Attribute Memory DMA)
- - [ ] PSG (Programmable Sound Generator)
+ - [x] PSG (Programmable Sound Generator)
  - [x] Timer
- - [ ] Link
+ - [x] Link (Dummy link module, allows some games to run in single player mode)
+
+Next step would be improving the accuracy.
+
+Photo of VerilogBoy on Pano G1 running open source GameBoy game [Tobu Tobu Girl](http://tangramgames.dk/tobutobugirl/):
+
+![Running-on-PanoG1](https://github.com/zephray/VerilogBoy/raw/refactor/doc/.png)
 
 For progress regarding different ports, view README.md under the specific target folder.
 

target/panog1/README.md

@@ -20,7 +20,7 @@ This port focus on the VGA version (3E-1600).
 
 ## Status
 
-Working in Progress
+Working in Progress. Preview version available in the GitHub 'Releases' section.
 
 ## Components
 
@@ -41,3 +41,39 @@ Configured as RV32IC, running at 25MHz.
 Currently, code is XIP from SPI Flash. SPI Flash also runs at 25MHz (Maximum frequency of M25P80 is 75MHz), 1 bit mode. A 4KB 2-way set associative cache is added between the PicoRV32 and SPI IF. Expect very poor performance.
 
 The PicoRV32 uses in total 8 BRAM18K for memories, 4 as scratchpad memory (8KB), 2 as I-cache (4KB), 2 as video RAM (4KB).
+
+## Building
+
+A modern Linux environment is required to build the firmware for the PicoRV32 soft processor. ISE version 14.7 is required to build the bitstream for the FPGA, WebPACK version is fine. ISE doesn't need to be installed on the Linux, it can be installed on a sepearate Windows machine, or inside a virtual machine.
+
+### Firmware
+
+Follow the instruction in the [PicoRV32 repository](https://github.com/cliffordwolf/picorv32) to install the riscv32ic toolchain.
+
+Cd into target/panog1/fw/firmware, run '''make'''. The firmware.bin is the target firmware.
+
+### BootROM
+
+A boot ROM is required to boot the VerilogBoy Core. Skip if you are not going to play GB games on it.
+
+[rgbds](https://github.com/rednex/rgbds) is required to build the boot ROM. Follow the instruction to install it.
+
+Cd into roms, run '''make'''. The bootrom.mif is the target firmware. Copy the file into target/panog1/fpga.
+
+### Bitstream
+
+Open target/panog1/fpga/panog1.xise using ISE, double click 'Generate Programming File', the pano_top.bit is the target bitstream.
+
+### Flash Image
+
+1. Open iMPACT, create a new project, and double click 'Create PROM File' on the left. 
+2. Select 'Configure Single FPGA' under 'SPI Flash' on the left. Click the right arrow button.
+3. Select '8M' as 'Storage Device (bits)', click 'Add Storage Device', and then click the right arrow button.
+4. Enter a file name, set 'Add Non-Configuration Data Files' to 'Yes'. Click 'OK'.
+5. Select the bitstream file. 
+6. When asked to add another device file, select 'No'.
+7. When asked to add data file, select 'Yes'
+8. Enter 'c0000' as the start address.
+9. Choose the 'firmware.bin'. (Not 'firmware.elf'!)
+10. Double click 'Generate File' on the left.
+11. Now the target mcs file should be generated. Flash it into the FPGA use iMPACT.