soc: adi: max32: Enable primary core to configure/start secondary core #84539
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Refactors the max32 soc family configuration to allow socs with cores other than arm cortex-m4. This will make it possible to add support for the secondary risc-v core that exists on some max32 variants. Signed-off-by: Maureen Helm <[email protected]>
Adds support for the primary m4 core to configure the boot address and start the clock for the secondary risc-v core. Unlike the msdk which defers this function to applications and requires users to copy/paste code from an msdk example application into their own application, in zephyr it is implemented in the common soc init routine of the primary core. It can be enabled/disabled and configured with Kconfig symbols and a devicetree chosen node, allowing applications to override board-level defaults if desired using overlays instead of modifying zephyr code. Signed-off-by: Maureen Helm <[email protected]>
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Adds support for the primary m4 core to configure the boot address and
start the clock for the secondary risc-v core. Unlike the msdk which
defers this function to applications and requires users to copy/paste
code from an msdk example application into their own application, in
zephyr it is implemented in the common soc init routine of the primary
core. It can be enabled/disabled and configured with Kconfig symbols and
a devicetree chosen node, allowing applications to override board-level
defaults if desired using overlays instead of modifying zephyr code.
Signed-off-by: Maureen Helm [email protected]