v0.4

lab4

new:

• support privilege mode
• add csr and mode register
• add error and interrupt support

updates:

• optimize forward route

TODO:

• optimize pipeline forward cpi
• optimize branch prediction

v0.3

lab3

updates:

• 4 associativities, 4 sets cache support

• add rv64im support, use DSP for multiplication

• optimize performances and get good scores on several benchmarks

TODO:

• optimize pipeline forward to support higher clock frequency

v0.2

lab2

updates:

• support random memory read/write delay
• support nearly all instructions of rv64i
• support memory alignment

v0.1

lab1

5-stage pipelined RISC-V64 processor with hazard module

limit support on rv64i

no forward module