Merge tag 'xilinx-for-v2022.01-rc1' of https://source.denx.de/u-boot/…

…custodians/u-boot-microblaze into next Xilinx changes for v2022.01-rc1 zynq: - Enable capsule update for qspi and mmc - Update zed DT qspi compatible string zynqmp: - Add missing modeboot for EMMC - Add missing nand DT properties - List all eeproms for SC on vck190 - Add vck190 SC psu_init clk: - Handle only GATE type clock for Versal watchdog: - Update versal driver to handle system reset
apalos · Sep 30, 2021 · 8bef036 · 8bef036
2 parents c8988ef + dced079
commit 8bef036
Show file tree

Hide file tree

Showing 19 changed files with 2,225 additions and 49 deletions.
diff --git a/.mailmap b/.mailmap
@@ -33,6 +33,7 @@ Jernej Skrabec <[email protected]> <[email protected]>
 Igor Opaniuk <[email protected]> <[email protected]>
 Igor Opaniuk <[email protected]> <[email protected]>
 Markus Klotzbuecher <[email protected]>
+Nicolas Saenz Julienne <[email protected]> <[email protected]>
 Patrice Chotard <[email protected]> <[email protected]>
 Patrick Delaunay <[email protected]> <[email protected]>
 Paul Burton <[email protected]> <[email protected]>

diff --git a/arch/arm/dts/armada-8040.dtsi b/arch/arm/dts/armada-8040.dtsi
@@ -40,7 +40,7 @@
 };
 
 &cp0_pinctl {
-	compatible = "marvell,mvebu-pinctrl", "marvell,8k-cpm-pinctrl";
+	compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cpm-pinctrl";
 	bank-name ="cp0-110";
 
 	cp0_i2c0_pins: cp0-i2c-pins-0 {
@@ -75,7 +75,7 @@
 };
 
 &cp1_pinctl {
-	compatible = "marvell,mvebu-pinctrl", "marvell,8k-cps-pinctrl";
+	compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cps-pinctrl";
 	bank-name ="cp1-110";
 
 	cp1_ge1_rgmii_pins: cp1-ge-rgmii-pins-0 {

diff --git a/arch/arm/dts/imx7d-sdb.dts b/arch/arm/dts/imx7d-sdb.dts
@@ -44,9 +44,9 @@
 		compatible = "spi-gpio";
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_spi4>;
-		gpio-sck = <&gpio1 13 GPIO_ACTIVE_LOW>;
-		gpio-mosi = <&gpio1 9 GPIO_ACTIVE_LOW>;
-		cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+		gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+		gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+		cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
 		num-chipselects = <1>;
 		#address-cells = <1>;
 		#size-cells = <0>;

diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts
@@ -53,7 +53,7 @@
 	status = "okay";
 	num-cs = <1>;
 	flash@0 {
-		compatible = "spansion,s25fl256s", "jedec,spi-nor";
+		compatible = "spansion,s25fl256s1", "jedec,spi-nor";
 		reg = <0>;
 		spi-max-frequency = <30000000>;
 		m25p,fast-read;

diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -24,6 +24,9 @@
 		i2c1 = &i2c1;
 		mmc0 = &sdhci1;
 		nvmem0 = &eeprom;
+		nvmem1 = &eeprom_ebm;
+		nvmem2 = &eeprom_fmc1;
+		nvmem3 = &eeprom_fmc2;
 		rtc0 = &rtc;
 		serial0 = &uart0;
 		serial1 = &dcc;
@@ -477,20 +480,32 @@
 				silabs,skip-recall;
 			};
 			/* and connector J212D */
+			eeprom_ebm: eeprom@52 { /* x-ebm module */
+				compatible = "st,24c128", "atmel,24c128";
+				reg = <0x52>;
+			};
 		};
 		fmc1: i2c@1 { /* FMCP1_IIC */
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <1>;
 			/* FIXME connection to Samtec J51C */
 			/* expected eeprom 0x50 FMC cards */
+			eeprom_fmc1: eeprom@50 {
+				compatible = "st,24c128", "atmel,24c128";
+				reg = <0x50>;
+			};
 		};
 		fmc2: i2c@2 { /* FMCP2_IIC */
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <2>;
 			/* FIXME connection to Samtec J53C */
 			/* expected eeprom 0x50 FMC cards */
+			eeprom_fmc2: eeprom@50 {
+				compatible = "st,24c128", "atmel,24c128";
+				reg = <0x50>;
+			};
 		};
 		i2c@3 { /* DDR4_DIMM1 */
 			#address-cells = <1>;

diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -140,6 +140,8 @@
 		nand-ecc-algo = "bch";
 		nand-rb = <0>;
 		label = "main-storage-0";
+		nand-ecc-step-size = <1024>;
+		nand-ecc-strength = <24>;
 
 		partition@0 {	/* for testing purpose */
 			label = "nand-fsbl-uboot";
@@ -174,6 +176,8 @@
 		nand-ecc-algo = "bch";
 		nand-rb = <0>;
 		label = "main-storage-1";
+		nand-ecc-step-size = <1024>;
+		nand-ecc-strength = <24>;
 
 		partition@0 {	/* for testing purpose */
 			label = "nand1-fsbl-uboot";

diff --git a/arch/arm/mach-bcm283x/msg.c b/arch/arm/mach-bcm283x/msg.c
@@ -170,6 +170,12 @@ int bcm2711_notify_vl805_reset(void)
 	ALLOC_CACHE_ALIGN_BUFFER(struct msg_notify_vl805_reset,
 				 msg_notify_vl805_reset, 1);
 	int ret;
+	static int done = false;
+
+	if (done)
+		return 0;
+
+	done = true;
 
 	BCM2835_MBOX_INIT_HDR(msg_notify_vl805_reset);
 	BCM2835_MBOX_INIT_TAG(&msg_notify_vl805_reset->dev_addr,

diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
@@ -13,6 +13,7 @@
 #include <fdtdec.h>
 #include <fpga.h>
 #include <malloc.h>
+#include <memalign.h>
 #include <mmc.h>
 #include <watchdog.h>
 #include <wdt.h>
@@ -151,3 +152,37 @@ enum env_location env_get_location(enum env_operation op, int prio)
 		return ENVL_NOWHERE;
 	}
 }
+
+#if defined(CONFIG_SET_DFU_ALT_INFO)
+
+#define DFU_ALT_BUF_LEN                SZ_1K
+
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
+
+	if (env_get("dfu_alt_info"))
+		return;
+
+	memset(buf, 0, sizeof(buf));
+
+	switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
+	case ZYNQ_BM_SD:
+		snprintf(buf, DFU_ALT_BUF_LEN,
+			 "mmc 0:1=boot.bin fat 0 1;"
+			 "u-boot.img fat 0 1");
+		break;
+	case ZYNQ_BM_QSPI:
+		snprintf(buf, DFU_ALT_BUF_LEN,
+			 "sf 0:0=boot.bin raw 0 0x1500000;"
+			 "u-boot.img raw 0x%x 0x500000",
+			 CONFIG_SYS_SPI_U_BOOT_OFFS);
+		break;
+	default:
+		return;
+	}
+
+	env_set("dfu_alt_info", buf);
+	puts("DFU alt info setting: done\n");
+}
+#endif