Move MFHI and MFHI next to their definers (fixes unison-code#53)

Move MFHI and MFLO instructions next to their definers during 'uni import' for
the Mips target, to avoid interfering live ranges in the acc64 register class.
This is to prevent 'splitBlocks' from creating such interferences across block
boundaries (which would not be solvable by instruction scheduling).

src/unison/src/Unison/Target/Mips.hs

@@ -131,7 +131,8 @@ copies (f, cst, _, _, _, _) False t [r] _d [_u]
 
 -- Extend temporaries defined in acc64 with mflo and mfhi only
 copies _ False _ [] d us
-    | isNatural d && targetInst (oInstructions d) `elem` [MULT, MULTu, DIV, MADD] =
+    | isNatural d && targetInst (oInstructions d) `elem`
+      [PseudoMULT, PseudoMADD, PseudoMTLOHI, MULT, MULTu, DIV, MADD] =
       ([], replicate (length us) [])
 copies _ False t [] d us
     | isLow d  = ([mkNullInstruction, TargetInstruction MFLO], map (accCopy t) us)
@@ -435,6 +436,7 @@ transforms ImportPreLift = [peephole rs2ts,
                             peephole extractReturnRegs,
                             (\f -> foldReservedRegisters f (target, [])),
                             mapToOperation hideStackPointer,
+                            coupleAcc64Operations,
                             mapToOperation addAlternativeInstructions]
 
 transforms ImportPostLift = [peephole clobberRAInCall]

src/unison/src/Unison/Target/Mips/Transforms.hs

@@ -15,6 +15,7 @@ module Unison.Target.Mips.Transforms
      normalizeCallEpilogue,
      extractReturnRegs,
      hideStackPointer,
+     coupleAcc64Operations,
      addAlternativeInstructions,
      clobberRAInCall,
      insertGPDisp,
@@ -27,6 +28,8 @@ import MachineIR
 import Unison.Target.Mips.Common
 import Unison.Target.Mips.MipsRegisterDecl
 import Unison.Target.Mips.SpecsGen.MipsInstructionDecl
+import Unison.Target.Mips.SpecsGen.OperandInfo
+import Unison.Target.Mips.SpecsGen.MipsRegisterClassDecl
 
 -- | Gives patterns as sequences of instructions and replacements where
 -- | registers are transformed into temporaries
@@ -332,6 +335,31 @@ hideStackPointer o = o
 
 isStackPointer = isTargetReg SP
 
+
+{-
+    Moves MFHI and MFLO instructions next to their definers, to avoid
+    interfering live ranges in the acc64 register class. This is to prevent
+    'splitBlocks' from creating such interferences across block boundaries
+    (which would not be solvable by instruction scheduling).
+-}
+coupleAcc64Operations f @ Function {fCode = code} =
+  f {fCode = map coupleAcc64OprsInBlock code}
+
+coupleAcc64OprsInBlock b @ Block {bCode = code} =
+  foldl coupleAcc64UsersOf b (filter (isAcc64Instr snd) code)
+
+coupleAcc64UsersOf b d =
+  moveOperations (isMovableUserOf d) after (isIdOf d) b
+
+isMovableUserOf d u = isAcc64Instr fst u && isUser (oSingleDef d) u
+
+isAcc64Instr f SingleOperation {
+  oOpr = (Natural Linear {oIs = [TargetInstruction i]})} =
+  case f (operandInfo i) of
+    [TemporaryInfo {oiRegClass = RegisterClass ACC64}] -> True
+    _ -> False
+isAcc64Instr _ _ = False
+
 {-
     For each delay slot branch, add two alternative instructions: the original
     instruction (for which there is an ad-hoc constraint requiring something