Fix pointer sev-rich form issue

While creating a SEV from a pointer a bitcast instruction should be used
ONLY when the result is also a pointer. Otherwise we can face the
following sequence:
%v = bitcast T* to <1 x T*>
%s = extractlement <1 x T*> %v, <i32> %zero_idx
%e = some_user_of_T <T*> %s

The excessive ExtractElement instruction cannot be removed since llvm
SimplifyExtractElementInst does not support such pattern.

GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp

@@ -1,6 +1,6 @@
 /*========================== begin_copyright_notice ============================
 
-Copyright (C) 2020-2021 Intel Corporation
+Copyright (C) 2020-2023 Intel Corporation
 
 SPDX-License-Identifier: MIT
 
@@ -305,7 +305,8 @@ static Value *createScalarToVectorValue(Value *Scalar, Type *ReferenceType,
                                         Instruction *InsertBefore) {
   if (isa<UndefValue>(Scalar))
     return UndefValue::get(ReferenceType);
-  else if (isa<PointerType>(Scalar->getType())) {
+  else if (isa<PointerType>(Scalar->getType()) &&
+           isa<PointerType>(ReferenceType)) {
     auto Inner = getInnerPointerVectorNesting(ReferenceType);
     return new BitCastInst(
         Scalar, getTypeWithSingleElementVector(Scalar->getType(), Inner),

GenXIntrinsics/test/Adaptors/sev_ptr_reader.ll

@@ -0,0 +1,32 @@
+;=========================== begin_copyright_notice ============================
+;
+; Copyright (C) 2023 Intel Corporation
+;
+; SPDX-License-Identifier: MIT
+;
+;============================ end_copyright_notice =============================
+
+; UNSUPPORTED: llvm17, llvm18
+; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s
+
+define internal void @foo(i32** "VCSingleElementVector"="1" %v) #0 {
+entry:
+  ; CHECK: [[SEV:[^ ]+]] = bitcast <1 x i32*>* %v to i32**
+  ; CHECK: %ld.v = load i32*, i32** [[SEV]], align 8
+  ; CHECK: %ld.ex = load i32, i32* %ld.v, align 4
+  %ld.v = load i32*, i32** %v, align 8
+  %ld.ex = load i32, i32* %ld.v, align 4
+  ret void
+}
+
+define internal "VCSingleElementVector"="2" i64*** @bar(i64** "VCSingleElementVector"="2" %in, i64*** "VCSingleElementVector"="2" %out) #0 {
+entry:
+  ; CHECK: [[SEV:[^ ]+]] = bitcast <1 x i64**>* %out to i64***
+  ; CHECK: [[SEVIN:[^ ]+]] = extractelement <1 x i64**> %in, i64 0
+  ; CHECK: store i64** [[SEVIN]], i64*** [[SEV]], align 8
+  store i64** %in, i64*** %out, align 8
+  ; CHECK: ret <1 x i64**>* %out
+  ret i64*** %out
+}
+
+attributes #0 = { "VCFunction" }

GenXIntrinsics/test/Adaptors/sev_ptr_writer.ll

@@ -0,0 +1,29 @@
+;=========================== begin_copyright_notice ============================
+;
+; Copyright (C) 2023 Intel Corporation
+;
+; SPDX-License-Identifier: MIT
+;
+;============================ end_copyright_notice =============================
+
+; UNSUPPORTED: llvm17, llvm18
+; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s
+
+define internal void @foo(<1 x i32*>* %v) #0 {
+entry:
+  ; CHECK: %ld.v = load i32*, i32** %v, align 8
+  ; CHECK: %ld.ex = load i32, i32* %ld.v, align 4
+  %ld.v = load <1 x i32*>, <1 x i32*>* %v, align 8
+  %ex = extractelement <1 x i32*> %ld.v, i32 0
+  %ld.ex = load i32, i32* %ex, align 4
+  ret void
+}
+
+define internal <1 x i64**>* @bar(<1 x i64**> %in, <1 x i64**>* %out) #0 {
+entry:
+  ; CHECK: store i64** %in, i64*** %out, align 8
+  store <1 x i64**> %in, <1 x i64**>* %out, align 8
+  ret <1 x i64**>* %out
+}
+
+attributes #0 = { "VCFunction" }