[RTGTest] Add a few instructions

llvm · Jan 21, 2025 · fc18855 · fc18855
1 parent 30f9e93
commit fc18855
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diff --git a/include/circt/Dialect/RTGTest/IR/RTGTestOps.td b/include/circt/Dialect/RTGTest/IR/RTGTestOps.td
@@ -63,3 +63,86 @@ def ConstantTestOp : RTGTestOp<"constant_test", [
   let assemblyFormat = "type($result) attr-dict";
   let hasFolder = 1;
 }
+
+//===- Instruction Formats -------------------------------------------------===//
+
+class InstFormatIOpBase<string mnemonic, int opcode7, int funct3>
+  : RTGTestOp<"rv32i." # mnemonic, [InstructionOpInterface]> {
+
+  let arguments = (ins IntegerRegisterType:$rd,
+                       IntegerRegisterType:$rs,
+                       Imm12Type:$imm);
+
+  let assemblyFormat = "$rd `,` $rs `,` $imm attr-dict";
+
+  let extraClassDeclaration = [{
+    static void printInstructionBinary(llvm::raw_ostream &os,
+                                       ArrayRef<Attribute> operands) {
+      FoldAdaptor adaptor(operands);
+
+      auto binary = APInt(12, cast<Imm12Attr>(adaptor.getImm()).getValue())
+        .concat(APInt(5, cast<rtg::RegisterAttrInterface>(
+          adaptor.getRs()).getClassIndex()))
+        .concat(APInt(3, }] # funct3 # [{))
+        .concat(APInt(5, cast<rtg::RegisterAttrInterface>(
+          adaptor.getRd()).getClassIndex()))
+        .concat(APInt(7, }] # opcode7 # [{));
+
+      SmallVector<char> str;
+      binary.toStringUnsigned(str, 16);
+      os << str;
+    }
+
+    static void printInstructionAssembly(llvm::raw_ostream &os,
+                                         ArrayRef<Attribute> operands) {
+      FoldAdaptor adaptor(operands);
+
+      os << getOperationName().split('.').second << " "
+         << cast<rtg::RegisterAttrInterface>(adaptor.getRd())
+              .getRegisterAssembly()
+         << ", "
+         << cast<Imm12Attr>(adaptor.getImm()).getValue()
+         << "("
+         << cast<rtg::RegisterAttrInterface>(adaptor.getRs())
+              .getRegisterAssembly()
+         << ")";
+    }
+  }];
+}
+
+class InstFormatIImmOpBase<string mnemonic, int opcode7, int funct12>
+  : RTGTestOp<"rv32i." # mnemonic, [InstructionOpInterface]> {
+
+  let assemblyFormat = "attr-dict";
+
+  let extraClassDeclaration = [{
+    static void printInstructionBinary(llvm::raw_ostream &os,
+                                       ArrayRef<Attribute> operands) {
+      auto binary = APInt(12, }] # funct12 # [{)
+      .concat(APInt(13, 0))
+      .concat(llvm::APInt(7, }] # opcode7 # [{));
+
+      SmallVector<char> str;
+      binary.toStringUnsigned(str, 16);
+      os << str;
+    }
+
+    static void printInstructionAssembly(llvm::raw_ostream &os,
+                                         ArrayRef<Attribute> operands) {
+      os << getOperationName().split('.').second;
+    }
+  }];
+}
+
+//===- Instructions -------------------------------------------------------===//
+
+def RV32I_JALROp    : InstFormatIOpBase<"jalr",  0b1100111, 0b000>;
+
+def RV32I_LBOp      : InstFormatIOpBase<"lb",  0b0000011, 0b000>;
+def RV32I_LHOp      : InstFormatIOpBase<"lh",  0b0000011, 0b001>;
+def RV32I_LWOp      : InstFormatIOpBase<"lw",  0b0000011, 0b010>;
+def RV32I_LBUOp     : InstFormatIOpBase<"lbu", 0b0000011, 0b100>;
+def RV32I_LHUOp     : InstFormatIOpBase<"lhu", 0b0000011, 0b101>;
+
+def RV32I_ECALLOp   : InstFormatIImmOpBase<"ecall", 0b1110011, 0b000000000000>;
+def RV32I_EBREAKOp  : InstFormatIImmOpBase<"ebreak", 0b1110011, 0b000000000001>;
diff --git a/test/Dialect/RTGTest/IR/basic.mlir b/test/Dialect/RTGTest/IR/basic.mlir
@@ -96,6 +96,28 @@ rtg.test @immediates : !rtg.dict<> {
   rtgtest.immediate #rtgtest.imm32<3> : !rtgtest.imm32
 }
 
+// CHECK-LABEL: @instructions
+rtg.test @instructions : !rtg.dict<imm: !rtgtest.imm12, rd: !rtgtest.ireg, rs: !rtgtest.ireg> {
+// CHECK: ([[IMM:%.+]]: !rtgtest.imm12, [[RD:%.+]]: !rtgtest.ireg, [[RS:%.+]]: !rtgtest.ireg)
+^bb0(%imm: !rtgtest.imm12, %rd: !rtgtest.ireg, %rs: !rtgtest.ireg):
+  // CHECK: rtgtest.rv32i.jalr [[RD]], [[RS]], [[IMM]]
+  rtgtest.rv32i.jalr %rd, %rs, %imm
+  // CHECK: rtgtest.rv32i.lb [[RD]], [[RS]], [[IMM]]
+  rtgtest.rv32i.lb %rd, %rs, %imm
+  // CHECK: rtgtest.rv32i.lh [[RD]], [[RS]], [[IMM]]
+  rtgtest.rv32i.lh %rd, %rs, %imm
+  // CHECK: rtgtest.rv32i.lw [[RD]], [[RS]], [[IMM]]
+  rtgtest.rv32i.lw %rd, %rs, %imm
+  // CHECK: rtgtest.rv32i.lbu [[RD]], [[RS]], [[IMM]]
+  rtgtest.rv32i.lbu %rd, %rs, %imm
+  // CHECK: rtgtest.rv32i.lhu [[RD]], [[RS]], [[IMM]]
+  rtgtest.rv32i.lhu %rd, %rs, %imm
+  // CHECK: rtgtest.rv32i.ecall
+  rtgtest.rv32i.ecall
+  // CHECK: rtgtest.rv32i.ebreak
+  rtgtest.rv32i.ebreak
+}
+
 // -----
 
 rtg.test @immediateTooBig : !rtg.dict<> {