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Pull requests: llvm/circt

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Pull requests list

[ESI] Add hostmem write support to cosim ESI PyCDE Python CIRCT Design Entry API
#8059 opened Jan 9, 2025 by teqdruid • Draft
[RTG] Add simple linear scan register allocation pass RTG Involving the `rtg` dialect
#8058 opened Jan 9, 2025 by maerhart Loading…
[RTG] Add ISA assembly emission pass RTG Involving the `rtg` dialect
#8057 opened Jan 9, 2025 by maerhart Loading…
[RTGTest] Add a few instructions RTG Involving the `rtg` dialect
#8056 opened Jan 9, 2025 by maerhart Loading…
1
[LoopScheduleToCalyx] deduplicate groups within a ParOp.
#8055 opened Jan 9, 2025 by cgyurgyik Loading…
1
5
[RTGTest] Add representation for immediates RTG Involving the `rtg` dialect
#8053 opened Jan 9, 2025 by maerhart Loading…
[RTGTest] Improved register representation RTG Involving the `rtg` dialect
#8052 opened Jan 9, 2025 by maerhart Loading…
[SMT] Add bv2int op
#8049 opened Jan 9, 2025 by TaoBi22 Loading…
[MemoryBanking] Support memory banking forGetGlobalOp
#8047 opened Jan 9, 2025 by jiahanxie353 Loading…
11
[SMT] Parse SMT bitvector width as signed bug Something isn't working SMT
#8042 opened Jan 8, 2025 by TaoBi22 Loading…
[HW] Enable parametric polymorphism for module parameters
#8040 opened Jan 8, 2025 by bubblepipe42 Loading…
[LLHD] Removing llhd-sim tests LLHD
#8036 opened Jan 7, 2025 by teqdruid Loading…
3
[RTG] Add context resource attribute interface RTG Involving the `rtg` dialect
#8034 opened Jan 6, 2025 by maerhart Loading…
2
Convert ICE40 to BLIF
#8031 opened Jan 5, 2025 by darthscsi • Draft
[FIRRTL] Add View Intrinsic
#8026 opened Jan 3, 2025 by seldridge • Draft
[ImportVerilog] add real literal support, refine real type, and add real format support Moore
#8020 opened Dec 29, 2024 by chenbo-again • Draft
6
Add the BLIF dialect.
#8019 opened Dec 29, 2024 by darthscsi Loading…
4
Add the ICE40 dialect.
#8018 opened Dec 27, 2024 by darthscsi Loading…
11
[ImportVerilog] Add foreach statement support. Moore
#8017 opened Dec 26, 2024 by chenbo-again Loading…
9
[ImportVerilog] Support for Procedural assign statements ImportVerilog Moore
#8010 opened Dec 19, 2024 by owlxiao Loading…
2
[ImportVerilog] sva prototype ImportVerilog Moore
#7999 opened Dec 16, 2024 by chenbo-again • Draft
[RTG][Elaboration] Move ConstantLike check after TypeSwitch for better performance RTG Involving the `rtg` dialect
#7998 opened Dec 16, 2024 by maerhart Loading…
1
[RTG][Elaboration] Do not internalize primitive values RTG Involving the `rtg` dialect
#7997 opened Dec 16, 2024 by maerhart Loading…
[HW] Add pass to outline certain ops: hw-outline-ops HW Involving the `hw` dialect
#7991 opened Dec 13, 2024 by teqdruid Loading…
5
[RTG][Elaboration] Add support for 'scf.if' and 'scf.for' RTG Involving the `rtg` dialect
#7986 opened Dec 13, 2024 by maerhart Loading…
4
ProTip! What’s not been updated in a month: updated:<2024-12-09.