Add the ICE40 dialect. #8018
Add the ICE40 dialect. #8018
Conversation
The ICE40 dialect is a synthesis target representing the Lattice ICE40 family of fpgas.
|
Hobby or SiFive work? |
Hobby. Want to push things a bit and build on @uenoku 's synthesis work (also hobby, but hopefully I can fund it). |
| // SBLut4Op | ||
| //===----------------------------------------------------------------------===// | ||
|
|
||
| LogicalResult SBLut4Op::verify() { return success(); } |
There was a problem hiding this comment.
This is really exciting! One nit - is it worth verifying that lut_init has 16 elements? Or is this just a placeholder verifier
|
Would it be better to do it as a generic FPGA dialect? |
There's no way to capture all the details of every FPGA in a set of common ops. There is something to be said for one dialect containing ops for each FPGA family, but it's easier to start separately then merge dialects if need be. |
| carry_out(i0, i1, ci) = 1 iff popcount(concat(i0,i1,ci)) >= 2. | ||
| result(i0, i1, i2, i3) = lut_init[concat(i3,i2,i1,i0)]. | ||
| There are constraints on the use, as i0 and i1 have to be the i0 and i1 input of a single lut. | ||
| This op doesn't check this. There is a combined op that handles that. |
There was a problem hiding this comment.
Isn't this the combined op?
| // SBLut4Op | ||
| //===----------------------------------------------------------------------===// | ||
|
|
||
| LogicalResult SBLut4Op::verify() { return success(); } |
| // SBLut4CarryOp | ||
| //===----------------------------------------------------------------------===// | ||
|
|
||
| LogicalResult SBLut4CarryOp::verify() { return success(); } |
There was a problem hiding this comment.
Same comment re checking here.
| @@ -0,0 +1,11 @@ | |||
| // RUN: circt-opt %s | FileCheck %s | |||
There was a problem hiding this comment.
When you add the verifier, create an error test.
The ICE40 dialect is a synthesis target representing the Lattice ICE40 family of fpgas.