added JTAG busDef

[drom]

Here is a proposed JTAG bus Definition document.
I am looking for feedback on what additional signals related to JTAG should be included?
Related to #15

[Ramlakshmi3733]

much needed
Francois also needs to be aware so that it could be netbundle in ICC

[fferhani]

@drom can you explain the purpose of defining a JTAG bus in DUH? That would help me provide useful feedback.

[fferhani]

@drom if your purpose is to define all the possible DFT connections in a design you would also need IEEE 1687 and IEEE 1500 buses. I can define them for you if you want.

[fferhani]

@drom in case your purpose is to the DFT connections in a design you need to add the two buses below:

The IEEE 1500 Embedded Core Test signals:

1. WRCK: Wrapper Clock. Provides timing for the core wrapper signaling.
2. WSI: Wrapper Serial Input. Serial input to the 1500 Wrapper Serial Port (WSP)
3. WSO: Wrapper Serial Output. Serial output from the 1500 Wrapper Serial Port
4. WRSTN: Wrapper Reset. Resets the wrapper.
5. ShiftWR: Wrapper Shift. The Shift Enable signal for the active 1500 Wrapper Scan Path registers.
6. CaptureWR: Wrapper Capture. The Capture Enable signals for the active 1500 Wrapper Scan Path
   registers.
7. UpdateWR: Wrapper Update. The Update Enable signal for the active 1500 Wrapper Scan Path registers.
8. SelectWIR: Select Wrapper Instruction Register. Activates an instruction register as the active Wrapper Scan Path register.

The IEEE 1687 IJTAG signals:

1. ijtag_tck: clock
2. ijtag_reset: reset
3. ijtag_ce: capture
4. ijtag_se: shift
5. ijtag_sel: select
6. ijtag_si: scan data in
7. ijtag_ue: update

[drom]

The IEEE 1500 Embedded Core Test signals:

1. WRCK: Wrapper Clock. Provides timing for the core wrapper signaling.
2. WSI: Wrapper Serial Input. Serial input to the 1500 Wrapper Serial Port (WSP)
3. WSO: Wrapper Serial Output. Serial output from the 1500 Wrapper Serial Port
4. WRSTN: Wrapper Reset. Resets the wrapper.
5. ShiftWR: Wrapper Shift. The Shift Enable signal for the active 1500 Wrapper Scan Path registers.
6. CaptureWR: Wrapper Capture. The Capture Enable signals for the active 1500 Wrapper Scan Path
   registers.
7. UpdateWR: Wrapper Update. The Update Enable signal for the active 1500 Wrapper Scan Path registers.
8. SelectWIR: Select Wrapper Instruction Register. Activates an instruction register as the active Wrapper Scan Path register.

Added separate issue: #18

[drom]

The IEEE 1687 IJTAG signals:

1. ijtag_tck: clock
2. ijtag_reset: reset
3. ijtag_ce: capture
4. ijtag_se: shift
5. ijtag_sel: select
6. ijtag_si: scan data in
7. ijtag_ue: update

Added separate issue: #19

[drom]

@drom can you explain the purpose of defining a JTAG bus in DUH? That would help me provide useful feedback.

While onboarding or developing IP blocks, we should be able to map ports as "bus interfaces" of a specific type. For this purpose, we have to create "bus definition" (like a type signature) that would provide a set of rules/constraints associated with this interface type. Later when composing SoC out of specific IP clocks we can automate the discovery of specific interfaces, creation, and validation of appropriate infrastructure.