Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Fix PLLSrc enum not matching capitalisation conventions #131

Merged
merged 1 commit into from
Aug 5, 2024
Merged

Fix PLLSrc enum not matching capitalisation conventions #131

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion examples/flash_with_rtic.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -48,7 +48,7 @@ mod app {
let mut pll_config = stm32g4xx_hal::rcc::PllConfig::default();

// Sysclock is based on PLL_R
pll_config.mux = stm32g4xx_hal::rcc::PLLSrc::HSI; // 16MHz
pll_config.mux = stm32g4xx_hal::rcc::PllSrc::HSI; // 16MHz
pll_config.n = stm32g4xx_hal::rcc::PllNMul::MUL_32;
pll_config.m = stm32g4xx_hal::rcc::PllMDiv::DIV_2; // f(vco) = 16MHz*32/2 = 256MHz
pll_config.r = Some(stm32g4xx_hal::rcc::PllRDiv::DIV_2); // f(sysclock) = 256MHz/2 = 128MHz
Expand Down
6 changes: 3 additions & 3 deletions src/rcc/config.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,7 @@ pub enum LSCOSrc {

/// PLL clock input source
#[derive(Clone, Copy)]
pub enum PLLSrc {
pub enum PllSrc {
HSI,
HSE(Hertz),
HSE_BYPASS(Hertz),
Expand Down Expand Up @@ -304,7 +304,7 @@ impl PllNMul {
/// PLL config
#[derive(Clone, Copy)]
pub struct PllConfig {
pub mux: PLLSrc,
pub mux: PllSrc,
pub m: PllMDiv,
pub n: PllNMul,
pub r: Option<PllRDiv>,
Expand All @@ -315,7 +315,7 @@ pub struct PllConfig {
impl Default for PllConfig {
fn default() -> PllConfig {
PllConfig {
mux: PLLSrc::HSI,
mux: PllSrc::HSI,
m: PllMDiv::DIV_2,
n: PllNMul::MUL_8,
r: Some(PllRDiv::DIV_2),
Expand Down
6 changes: 3 additions & 3 deletions src/rcc/mod.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -244,15 +244,15 @@ impl Rcc {

// Enable the input clock feeding the PLL
let (pll_input_freq, pll_src_bits) = match pll_cfg.mux {
PLLSrc::HSI => {
PllSrc::HSI => {
self.enable_hsi();
(HSI_FREQ, 0b10)
}
PLLSrc::HSE(freq) => {
PllSrc::HSE(freq) => {
self.enable_hse(false);
(freq.raw(), 0b11)
}
PLLSrc::HSE_BYPASS(freq) => {
PllSrc::HSE_BYPASS(freq) => {
self.enable_hse(true);
(freq.raw(), 0b11)
}
Expand Down
Loading