Implemented last registers

crates/ads126x/src/lib.rs

@@ -6,7 +6,7 @@ mod register;
 
 use error::ADS126xError;
 use register::{
-    GpioConRegister, GpioDatRegister, GpioDirRegister, IdRegister, IdacMagRegister, IdacMuxRegister, InpMuxRegister, InterfaceRegister, Mode0Register, Mode1Register, Mode2Register, PowerRegister, RefMuxRegister, Register, TdacnRegister, TdacpRegister
+    Adc2CfgRegister, Adc2MuxRegister, GpioConRegister, GpioDatRegister, GpioDirRegister, IdRegister, IdacMagRegister, IdacMuxRegister, InpMuxRegister, InterfaceRegister, Mode0Register, Mode1Register, Mode2Register, PowerRegister, RefMuxRegister, Register, TdacnRegister, TdacpRegister
 };
 
 use embedded_hal::spi::FullDuplex;
@@ -213,43 +213,39 @@ where
     }
 
     pub fn get_ofcal(&mut self) -> Result<u32> {
-        let mut bytes = self.read_multiple_registers(Register::OFCAL0, 3)?; // [OFCAL0, OFCAL1, OFCAL2]
-        bytes.reverse(); // [OFCAL2, OFCAL1, OFCAL0]
-        let mut res: u32 = 0;
-        for &b in &bytes[3..0] {
-            res <<= 8; // Shift previous bits left one byte
-            res |= b as u32; // Append new byte to the end
-        }
+        let bytes = self.read_multiple_registers(Register::OFCAL0, 3)?; // [OFCAL0, OFCAL1, OFCAL2]
+        let res = (bytes[2] as u32) << 16 |
+                  (bytes[1] as u32) << 8 |
+                  (bytes[0] as u32);
         Ok(res)
     }
 
     pub fn set_ofcal(&mut self, ofcal: u32) -> Result<()> {
-        let mut bytes: [u8; 4] = [0; 4];
-        for i in 0..4 {
-            let b = (ofcal >> (8 * i)) & 0xFF; // Get desired byte
-            bytes[i] = u8::try_from(b).unwrap(); // Should not panic as & 0xFF ensures b is a u8
-        }
-        self.write_multiple_registers(Register::OFCAL0, &bytes[0..3])
+        // Will not panic as & 0xFF ensures values are u8
+        let res: [u8; 3] = [
+            u8::try_from(ofcal & 0xFF).unwrap(),
+            u8::try_from((ofcal >> 8) & 0xFF).unwrap(),
+            u8::try_from((ofcal >> 16) & 0xFF).unwrap(),
+        ];
+        self.write_multiple_registers(Register::OFCAL0, &res)
     }
 
     pub fn get_fscal(&mut self) -> Result<u32> {
-        let mut bytes = self.read_multiple_registers(Register::FSCAL0, 3)?; // [FSCAL0, FSCAL1, FSCAL2]
-        bytes.reverse(); // [FSCAL2, FSCAL1, FSCAL0]
-        let mut res: u32 = 0;
-        for &b in &bytes[3..0] {
-            res <<= 8; // Shift previous bits left one byte
-            res |= b as u32; // Append new byte to the end
-        }
+        let bytes = self.read_multiple_registers(Register::FSCAL0, 3)?; // [FSCAL0, FSCAL1, FSCAL2]
+        let res = (bytes[2] as u32) << 16 |
+                  (bytes[1] as u32) << 8 |
+                  (bytes[0] as u32);
         Ok(res)
     }
 
     pub fn set_fscal(&mut self, fscal: u32) -> Result<()> {
-        let mut bytes: [u8; 4] = [0; 4];
-        for i in 0..4 {
-            let b = (fscal >> (8 * i)) & 0xFF; // Get desired byte
-            bytes[i] = u8::try_from(b).unwrap(); // Should not panic as & 0xFF ensures b is a u8
-        }
-        self.write_multiple_registers(Register::FSCAL0, &bytes[0..3])
+        // Will not panic as & 0xFF ensures values are u8
+        let res: [u8; 3] = [
+            u8::try_from(fscal & 0xFF).unwrap(),
+            u8::try_from((fscal >> 8) & 0xFF).unwrap(),
+            u8::try_from((fscal >> 16) & 0xFF).unwrap(),
+        ];
+        self.write_multiple_registers(Register::FSCAL0, &res)
     }
 
     pub fn get_idacmux(&mut self) -> Result<IdacMuxRegister> {
@@ -355,4 +351,63 @@ where
     pub fn set_gpiodat(&mut self, reg: &GpioDatRegister) -> Result<()> {
         self.write_register(Register::GPIODAT, reg.bits())
     }
+
+    pub fn get_adc2cfg(&mut self) -> Result<Adc2CfgRegister> {
+        let bits = self.read_register(Register::ADC2CFG)?;
+        let data = Adc2CfgRegister::from_bits(bits);
+        match data {
+            Some(reg) => Ok(reg),
+            None => Err(ADS126xError::InvalidInputData),
+        } 
+    }
+
+    pub fn set_adc2cfg(&mut self, reg: &Adc2CfgRegister) -> Result<()> {
+        self.write_register(Register::ADC2CFG, reg.bits())
+    }
+
+
+    pub fn get_adc2mux(&mut self) -> Result<Adc2MuxRegister> {
+        let bits = self.read_register(Register::ADC2MUX)?;
+        let data = Adc2MuxRegister::from_bits(bits);
+        match data {
+            Some(reg) => Ok(reg),
+            None => Err(ADS126xError::InvalidInputData),
+        } 
+    }
+
+    pub fn set_adc2mux(&mut self, reg: &Adc2MuxRegister) -> Result<()> {
+        self.write_register(Register::ADC2MUX, reg.bits())
+    }
+
+    pub fn get_adc2ofc(&mut self) -> Result<u16> {
+        let bytes = self.read_multiple_registers(Register::ADC2OFC0, 2)?; // [ADC2OFC0, ADC2OFC1]
+        let res = (bytes[1] as u16) << 8 |
+                  (bytes[0] as u16);
+        Ok(res)
+    }
+
+    pub fn set_adc2ofc(&mut self, ofc2: u16) -> Result<()> {
+        // Will not panic as & 0xFF ensures values are u8
+        let res: [u8; 2] = [
+            u8::try_from(ofc2 & 0xFF).unwrap(),
+            u8::try_from((ofc2 >> 8) & 0xFF).unwrap(),
+        ];
+        self.write_multiple_registers(Register::ADC2OFC0, &res)
+    }
+
+    pub fn get_adc2fsc(&mut self) -> Result<u16> {
+        let bytes = self.read_multiple_registers(Register::ADC2FSC0, 2)?; // [ADC2FSC0, ADC2FSC1]
+        let res = (bytes[1] as u16) << 8 |
+                  (bytes[0] as u16);
+        Ok(res)
+    }
+
+    pub fn set_adc2fsc(&mut self, fsc2: u32) -> Result<()> {
+        // Will not panic as & 0xFF ensures values are u8
+        let res: [u8; 2] = [
+            u8::try_from(fsc2 & 0xFF).unwrap(),
+            u8::try_from((fsc2 >> 8) & 0xFF).unwrap(),
+        ];
+        self.write_multiple_registers(Register::ADC2FSC0, &res)
+    }
 }

crates/ads126x/src/register.rs

@@ -591,3 +591,129 @@ bitflags! {
         const DAT7 = 0b1000_0000;
     }
 }
+
+bitflags! {
+    pub struct Adc2CfgRegister: u8 {
+        const _ = !0; // Source may set any bits
+    }
+}
+
+impl Adc2CfgRegister {
+    pub fn get_gain2(&self) -> Adc2Gain {
+        match self.bits() & 0b0000_0111 {
+            0b000 => Adc2Gain::VV1,
+            0b001 => Adc2Gain::VV2,
+            0b010 => Adc2Gain::VV4,
+            0b011 => Adc2Gain::VV8,
+            0b100 => Adc2Gain::VV16,
+            0b101 => Adc2Gain::VV32,
+            0b110 => Adc2Gain::VV64,
+            0b111 => Adc2Gain::VV128,
+
+            _ => unreachable!(),
+        }
+    }
+
+    pub fn set_gain2(&mut self, gain2: Adc2Gain) {
+        let bits = gain2 as u8;
+        self.insert(Adc2CfgRegister::from_bits_retain(bits));
+    }
+
+    pub fn get_ref2(&self) -> Adc2RefInp {
+        match (self.bits() & 0b0011_1000) >> 3 {
+            0b000 => Adc2RefInp::Int2_5VRef,
+            0b001 => Adc2RefInp::ExtAIN0_1,
+            0b010 => Adc2RefInp::ExtAIN2_3,
+            0b011 => Adc2RefInp::ExtAIN4_5,
+            0b100 => Adc2RefInp::IntAnlgSup,
+
+            0b101..=0b111 => panic!("Reserved ADC2 reference input"),
+            _ => unreachable!(),
+        }
+    }
+
+    pub fn set_ref2(&mut self, ref2: Adc2RefInp) {
+        let bits = ref2 as u8;
+        self.insert(Adc2CfgRegister::from_bits_retain(bits << 3));
+    }
+
+    pub fn get_dr2(&self) -> Adc2DataRate {
+        match (self.bits() & 0b1100_0000) >> 6 {
+            0b00 => Adc2DataRate::SPS10,
+            0b01 => Adc2DataRate::SPS100,
+            0b10 => Adc2DataRate::SPS400,
+            0b11 => Adc2DataRate::SPS800,
+
+            _ => unreachable!(),
+        }
+    }
+
+    pub fn set_dr2(&mut self, dr2: Adc2DataRate) {
+        let bits = dr2 as u8;
+        self.insert(Adc2CfgRegister::from_bits_retain(bits << 6));
+    }
+}
+
+bitflags! {
+    pub struct Adc2MuxRegister: u8 {
+        const _ = !0; // Source may set any bits
+    }
+}
+
+impl Adc2MuxRegister {
+    pub fn get_muxn2(&self) -> NegativeInpMux {
+        match self.bits() & 0b0000_1111 {
+            0b0000 => NegativeInpMux::AIN0,
+            0b0001 => NegativeInpMux::AIN1,
+            0b0010 => NegativeInpMux::AIN2,
+            0b0011 => NegativeInpMux::AIN3,
+            0b0100 => NegativeInpMux::AIN4,
+            0b0101 => NegativeInpMux::AIN5,
+            0b0110 => NegativeInpMux::AIN6,
+            0b0111 => NegativeInpMux::AIN7,
+            0b1000 => NegativeInpMux::AIN8,
+            0b1001 => NegativeInpMux::AIN9,
+            0b1010 => NegativeInpMux::AINCOM,
+            0b1011 => NegativeInpMux::TempSensMonNeg,
+            0b1100 => NegativeInpMux::AnlgPwrSupMonNeg,
+            0b1101 => NegativeInpMux::DgtlPwrSubMonNeg,
+            0b1110 => NegativeInpMux::TDACTestSignalNeg,
+            0b1111 => NegativeInpMux::Float,
+
+            _ => unreachable!(),
+        }
+    }
+
+    pub fn set_muxn2(&mut self, muxn2: NegativeInpMux) {
+        let bits = muxn2 as u8;
+        self.insert(Adc2MuxRegister::from_bits_retain(bits));
+    }
+
+    pub fn get_muxp2(&self) -> PositiveInpMux {
+        match (self.bits() & 0b1111_0000) >> 4 {
+            0b0000 => PositiveInpMux::AIN0,
+            0b0001 => PositiveInpMux::AIN1,
+            0b0010 => PositiveInpMux::AIN2,
+            0b0011 => PositiveInpMux::AIN3,
+            0b0100 => PositiveInpMux::AIN4,
+            0b0101 => PositiveInpMux::AIN5,
+            0b0110 => PositiveInpMux::AIN6,
+            0b0111 => PositiveInpMux::AIN7,
+            0b1000 => PositiveInpMux::AIN8,
+            0b1001 => PositiveInpMux::AIN9,
+            0b1010 => PositiveInpMux::AINCOM,
+            0b1011 => PositiveInpMux::TempSensMonPos,
+            0b1100 => PositiveInpMux::AnlgPwrSupMonPos,
+            0b1101 => PositiveInpMux::DgtlPwrSubMonPos,
+            0b1110 => PositiveInpMux::TDACTestSignalPos,
+            0b1111 => PositiveInpMux::Float,
+
+            _ => unreachable!(),
+        }
+    }
+
+    pub fn set_muxp2(&mut self, muxp2: PositiveInpMux) {
+        let bits = muxp2 as u8;
+        self.insert(Adc2MuxRegister::from_bits_retain(bits << 4));
+    }
+}

crates/ads126x/src/register/enums.rs

@@ -231,3 +231,32 @@ pub enum TdacOutMag {
     V1_5       = 0b11000,
     V0_5       = 0b11001,
 }
+
+#[repr(u8)]
+pub enum Adc2Gain {
+    VV1   = 0b000,
+    VV2   = 0b001,
+    VV4   = 0b010,
+    VV8   = 0b011,
+    VV16  = 0b100,
+    VV32  = 0b101,
+    VV64  = 0b110,
+    VV128 = 0b111,
+}
+
+#[repr(u8)]
+pub enum Adc2RefInp {
+    Int2_5VRef = 0b000,
+    ExtAIN0_1  = 0b001,
+    ExtAIN2_3  = 0b010,
+    ExtAIN4_5  = 0b011,
+    IntAnlgSup = 0b100,
+}
+
+#[repr(u8)]
+pub enum Adc2DataRate {
+    SPS10    = 0b00,
+    SPS100   = 0b01,
+    SPS400   = 0b10,
+    SPS800   = 0b11,
+}