Ibex bumped to CHERIoT ISA v1 #383
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Update code from upstream repository https://github.com/lowrisc/cheriot-ibex.git to revision 515481d29a4b927548498bd314a704340adb1ca3 * Verilator width resolution (Marno van der Maas) * Nix formatting (Marno van der Maas) * Feed RV32M through ibexc_top_tracing/ibexc_top (Greg Chadwick) * Switch to no bitmanip by default (Greg Chadwick) * RV32B parameter now passed in ibexc_top (Marno van der Maas) * Add UNOPTFLAT waiver to ibex_id_stage (Adrian Lees) * Patched prim_arbiter.vlt file (Adrian Lees) * Patch to add UNOPTFLAT waiver to prim_arbiter_ppc (Adrian Lees) * [rtl] Fix ICache scramble key valid input (Greg Chadwick) * [rtl] Enable use of ICache with ibexc_top (Greg Chadwick) * [util] Update check_tool_requirements.py (Gary Guo) * Update lowrisc_ip to lowRISC/opentitan@f235838a9e (Marno van der Maas) * Added patch to remove alert prim from all group (Marno van der Maas) * [vendor] Patch updated based on OpenTitan/36a2d3c (Marno van der Maas) * [dv] Alter cov_merge.tcl patch so icache coverage collection works (Greg Chadwick) * Add patch for lowrisc_ip (Harry Callahan) * [vendor] Update patch file based on upstream OpenTitan (Marno van der Maas) * Feed CHERI errors out to top module (Marno van der Maas) * Remove prim alert from build (Marno van der Maas) * Fix tracing (Marno van der Maas) * Update two port RAM for Sonata (Marno van der Maas) * Patch reading memory files taken from upstream (Marno van der Maas) * Various Verilator lint patches (Marno van der Maas) * Use ibexc_top since that is used in SAFE (Marno van der Maas) * Add FPGA primitives (Marno van der Maas) * Bump jinja2 from 3.1.4 to 3.1.5 in /dv/formal (dependabot[bot]) * Bump mako from 1.1.6 to 1.2.2 in /dv/formal (dependabot[bot]) * Formal verification flow for CHERIoT Ibex (mndstrmr) * fixed typos in previous commit (cheri_regfile) (kliuMsft) * fixed issue lowrisc/cheriot-ibex#59 (kliuMsft) * added support for the new cap bounds encoding (implict T8) and the corresponding top-level parameter CheriCapIT8 (kliuMsft) * Minor fixes in ibex_tracer for rv32 mode (kliuMsft) * Add default parameters to fix build under Xcelium (Greg Chadwick) * Update GitHub upload-artifact action to v4 (Nathaniel Wesley Filardo) * minor sv style cleanup (kliuMsft) * changes to align with ISA 1.0 release (kliuMsft) * Base correction only needs one bit (Marno van der Maas) * fixed rvfi_rd_addr for c.srai64 and c.slli64 (kliuMsft) * fixed bit extension instr decoding (issue lowrisc/cheriot-ibex#47) (kliuMsft) * fixed decoder for illegal_reg_cheri/rv32e generation in the case of use_rs3 instructions (kliuMsft) * PVIO needs 3 bit indexes not 4 (Marno van der Maas) * cheri_ex_err_info flop signals weren't used (Marno van der Maas) * added another yml (Nazerke Turtayeva) * adding files (Nazerke Turtayeva) Signed-off-by: Marno van der Maas <[email protected]>
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elliotb-lowrisc
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Jan 23, 2025
These are introduced upstream and are relatively harmless.
marnovandermaas
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Hopefully that's better. |
This is introduced upstream and mainly indicates that Verilator cannot simulate this efficiently. Functionality is fine though.
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This brings our CHERIoT Ibex up to ISA v1. This is the last part that is necessary for making Sonata v1.1 release.